11-05-2014 05:48 AM
I need to implement a TDR (Time Division Reflectometer) for cable fault detection using the ML605.
My sistem should provide:
* High speed ADC > 1Gsps
* High speed DAC > 1Gsps
* Countinuous acquisition for at least 10 us @ 1Gsps (which is enough to test a 900 m cable with 60% velocity factor)
* Data buffered during acquisition and sent to a host PC for DSPing once acquisiton is completed.
The FMC160 AD/DA seem to provide enough time accuracy and is compatible with the ML605. Are there any reference designs I could start with? Any idea if the DDR3 is suitable to work as a temporary buffer between ADC and PC? Is it possible to use the USB2UART instead of PCI to trasfer all that mass of data?
Every suggestions would be appreciated.
11-18-2014 04:44 AM
I did not find any example reference design in Xilinx web site for TDR (Time Division Reflectometer) for cable fault detection using the ML605
The below ML605 board link shows the all Xilinx provided example reference designs
11-18-2014 07:33 AM
Thank you Umamahe.
Bui what is happening with Xilinx website? Most of the page I used to visit are no longer available...
11-21-2014 04:12 AM - edited 11-21-2014 04:13 AM
The Xilinx boards web site changed recently. Please open the below link
Then check the required field boxes like example designs, Reference designs etc.