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Observer aliasnikhil
Observer
3,930 Views
Registered: ‎06-06-2012

ML605: Number of I/Os

Hi,

 

I am trying to test my design on ML605 board. Currently, I am using hardware Co-simulation to provide my input test vectors to my design. But if my inputs are externally generated, how do I give them to the FPGA? The number of bits I give as input is more than 12bits. My design runs at 200MHz.

 

Thanks!

-Nik

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2 Replies
Xilinx Employee
Xilinx Employee
3,918 Views
Registered: ‎11-28-2007

Re: ML605: Number of I/Os

You will need to create non memory mapped IOs for your hardware cosim token:

 

http://myfpgablog.blogspot.com/2009/12/sysgen-create-new-hwcosim-target-with.html


@aliasnikhil wrote:

Hi,

 

I am trying to test my design on ML605 board. Currently, I am using hardware Co-simulation to provide my input test vectors to my design. But if my inputs are externally generated, how do I give them to the FPGA? The number of bits I give as input is more than 12bits. My design runs at 200MHz.

 

Thanks!

-Nik




Cheers,
Jim
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Observer aliasnikhil
Observer
3,914 Views
Registered: ‎06-06-2012

Re: ML605: Number of I/Os

Hi Jim,

 

I have read your blog before. But I want to know how many pins can I use this way as I/O and where can I find them on the board? Also, is it possible to make it run without hardware co-simulation? I am not exchanging any data with Simulink. It is using a free-running 200MHz differential clock on the ML605 board. For using this 200MHz clock, I have to create a netlist with sysgen and edit the netlist of clock wrapper as you have suggested me on another thread.

 

Thanks!

-Nik

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