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Visitor wltuestc
Visitor
4,194 Views
Registered: ‎07-06-2011

ML605 Slave SelectMap Configuration

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Hi,

         I think the ML605 board can use Slave SelectMap configuration mode to configure the FPGA. But i am confused with the pull up and pull down resistors. Such as the FPGA_CCLK is pulled up with a 100 resistor and pulled down with a 100 resistor at the same time, PLATFLASH_FCS_B is pulled up with 4.7K resistor. But in Platform Flash XL Configuration and Storage Device User Guide(UG438), there no pull up or pull down resistors when connect cclk to K, FCS_B is pulled down using one 1k resistor. The resistors used by FPGA_FOE_B is 4.7k, but in UG438 is 1k. I do not know which is right , why?

        Thank you!

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Xilinx Employee
Xilinx Employee
5,275 Views
Registered: ‎09-22-2008

Re: ML605 Slave SelectMap Configuration

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  • 100 resistor and pulled down with a 100 resistor recommended for thevenin termination in which parallel combination matches with characteristic impedance. Signal integrity point of it is suitable where lower signal integrity requires.  Most of the cases for clocks signals this thevenin termination technique suitable

 

  • FCS_B is the active-Low to chip enable signal. Connect the Platform flash E# pin to the FPGA FCS_B pin. Connect this input to an external pull-down resistor to keep E# Low throughout the configuration process. So in case of using platform flash pull-down resistor is correct. For FPGA designs that do not use the platform flash, the FPGA design must drive FCS_B High to disable that perticular Platform flash. In that case the signal FCS_B to be pulled high

 

  • FOE_B is the active-Low output enable platform flash,. Connect the Platform flash G# pin to the FPGA FOE_B pin. Connect this input to an external pull-down resistor to keep G#Low throughout the configuration process. So in case of using platform flash pull-down resistor is correct. For FPGA designs that do not use the Platform flash, the FPGA design must drive FOE_B High to disable the Platform flash. In that case the signal FOE_B to be pulled high

Regards

Mahesh

 

If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

 

Mahesh

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3 Replies
Observer rho88
Observer
4,181 Views
Registered: ‎06-22-2011

Re: ML605 Slave SelectMap Configuration

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Xilinx recommends that you terminate CCLK for good signal integrity, which is what those 100 Ohms resistors are for.  In UG438 (figure 2-1) there is a note on CCLK that says the following:

"CCLK signal integrity is critical. Route and terminate the CCLK signal appropriately
to ensure good signal integrity at the XCF128X K pin and at the FPGA CCLK pin."

Remember that the ML605 can have multiple confiruation modes so they probably needed to adjust the resistors accordingly.  However, I would stay away from fully following the development board designs since Xilinx designs those so early in a products life cycle there are likely to be many differences in the user guide and what was implemented on the development boards.  Yes they are a good guideline, but always consult the user guide and datasheet first as these should contain all the latest information you need for your development. 

 

 

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Visitor wltuestc
Visitor
4,169 Views
Registered: ‎07-06-2011

Re: ML605 Slave SelectMap Configuration

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Hi, in UG438, we got that after configuration the FPGA design must drive the FPGA FCS_B pin High to disable the XCF128X . How can i do this, may the IO_L14P_FCS_B_24_Y24 pin be used as normal io after configuration and be directly drived to high level?

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Xilinx Employee
Xilinx Employee
5,276 Views
Registered: ‎09-22-2008

Re: ML605 Slave SelectMap Configuration

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  • 100 resistor and pulled down with a 100 resistor recommended for thevenin termination in which parallel combination matches with characteristic impedance. Signal integrity point of it is suitable where lower signal integrity requires.  Most of the cases for clocks signals this thevenin termination technique suitable

 

  • FCS_B is the active-Low to chip enable signal. Connect the Platform flash E# pin to the FPGA FCS_B pin. Connect this input to an external pull-down resistor to keep E# Low throughout the configuration process. So in case of using platform flash pull-down resistor is correct. For FPGA designs that do not use the platform flash, the FPGA design must drive FCS_B High to disable that perticular Platform flash. In that case the signal FCS_B to be pulled high

 

  • FOE_B is the active-Low output enable platform flash,. Connect the Platform flash G# pin to the FPGA FOE_B pin. Connect this input to an external pull-down resistor to keep G#Low throughout the configuration process. So in case of using platform flash pull-down resistor is correct. For FPGA designs that do not use the Platform flash, the FPGA design must drive FOE_B High to disable the Platform flash. In that case the signal FOE_B to be pulled high

Regards

Mahesh

 

If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

 

Mahesh

View solution in original post