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Explorer
Explorer
941 Views
Registered: ‎02-27-2018

Management of clocks coming from an FMC connector to an FPGA

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Hello,

I will be using the AC701 FPGA board. https://www.xilinx.com/support/documentation/boards_and_kits/ac701/ug952-ac701-a7-eval-bd.pdf

I need to use the pins of the FMC connector to connect the outputs of 8 ADC to the inputs of the FPGA ( 41 pairs of LVDS signals) 9 of these 41 pairs are LVDS clocks used in my design to sample data. My question is can i tie these signals to any I/O user pins of an H/R bank? Or do i have to tie these signals to special pins on the FPGA that can manage clocks? The AC701 board includes a Artix 7 xc7a200, Here is a figure that shows the pinout of the Artix 7.

I don't know where to look to determine if a pair of pins can handle an LVDS pair clock signal. Here is also a figure that shows the clocks out one 1 ADC (there are 8 in total) that i want to use as inputs to my FPGA:

Here is a figure of the FMC connector:

Thank you for your help

AC701pins.png
FMC VITA.png
dual_lane_quad_lane.png
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1 Solution

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Historian
Historian
1,360 Views
Registered: ‎01-23-2009

Re: Management of clocks coming from an FMC connector to an FPGA

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A couple of things...

 

First, if you are planning to use fast input interfaces (and both 320Mbps and especially 640Mbps fall into this category) then you must carefully plan your interfaces. Interfaces at these speeds (particularly 640Mbps) can be very tricky, or potentially not even possible (with static capture) in all FPGAs. What rate are you planning to run at - I don't think 640Mbps in an A7 will work...

 

If they are possible, then you must do everything perfectly

  - the clocks must be on clock capable inputs

     - putting them on non-clock capable inputs and using CLOCK_DEDICATED_ROUTE=FALSE will not meet timing

  - all data associated with a clock must be in the same bank as the clock

     - even adjacent banks (using the MRCC) while architecturally legal results in significantly poorer performance and will not work at higher speeds

 

Failure to do either of these will result in an interface with poorer performance, and at high speeds will make otherwise possible interfaces impossible.

 

A clock capable pin is identified in the pin name with either the SRCC or MRCC suffix in them. In the device pinout view, the pins that are hexagonal are clock capable pins - there are 4 clock capable LVDS pairs per bank. While you are using LVDS (so there is no ambiguity), it is worth pointing out that if you are using single ended clocks, the clocks must go on the P side of the clock capable pair - the N side is not clock capable for a single ended input.

 

Avrum

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6 Replies
Scholar dpaul24
Scholar
914 Views
Registered: ‎08-07-2014

Re: Management of clocks coming from an FMC connector to an FPGA

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@lebowski,

 

You should have made this connection as per your intuition and see what would have happened in the PnR stage! :-)

 

Coming to your question...

My question is can i tie these signals to any I/O user pins of an H/R bank? Or do i have to tie these signals to special pins on the FPGA that can manage clocks?

If clk capable pins are available then clks should be connected to them.

If not available (which is more often the case in a practical design scenario), then you have connect the clk to a normal IO pin. In the XDC file you need to set the property CLOCK_DEDICATED_ROUTE to FALSE and then continue.

 

 

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Explorer
Explorer
906 Views
Registered: ‎02-27-2018

Re: Management of clocks coming from an FMC connector to an FPGA

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Thank you very much.

How can i know if the pins are clock capable? When i look at the pinout on VIVADO of the ARTIX xc7a200, i only see I/O user pins or GND pins or VREF pins or Config pins, but nothing relation to clock capable pins

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899 Views
Registered: ‎06-21-2017

Re: Management of clocks coming from an FMC connector to an FPGA

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If you look at the part on the schematic, there will be "MRCC" in the pin name.

Historian
Historian
1,361 Views
Registered: ‎01-23-2009

Re: Management of clocks coming from an FMC connector to an FPGA

Jump to solution

A couple of things...

 

First, if you are planning to use fast input interfaces (and both 320Mbps and especially 640Mbps fall into this category) then you must carefully plan your interfaces. Interfaces at these speeds (particularly 640Mbps) can be very tricky, or potentially not even possible (with static capture) in all FPGAs. What rate are you planning to run at - I don't think 640Mbps in an A7 will work...

 

If they are possible, then you must do everything perfectly

  - the clocks must be on clock capable inputs

     - putting them on non-clock capable inputs and using CLOCK_DEDICATED_ROUTE=FALSE will not meet timing

  - all data associated with a clock must be in the same bank as the clock

     - even adjacent banks (using the MRCC) while architecturally legal results in significantly poorer performance and will not work at higher speeds

 

Failure to do either of these will result in an interface with poorer performance, and at high speeds will make otherwise possible interfaces impossible.

 

A clock capable pin is identified in the pin name with either the SRCC or MRCC suffix in them. In the device pinout view, the pins that are hexagonal are clock capable pins - there are 4 clock capable LVDS pairs per bank. While you are using LVDS (so there is no ambiguity), it is worth pointing out that if you are using single ended clocks, the clocks must go on the P side of the clock capable pair - the N side is not clock capable for a single ended input.

 

Avrum

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Explorer
Explorer
810 Views
Registered: ‎02-27-2018

Re: Management of clocks coming from an FMC connector to an FPGA

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Thank you for the clear answer.

 

If they are possible, then you must do everything perfectly

  - the clocks must be on clock capable inputs

     - putting them on non-clock capable inputs and using CLOCK_DEDICATED_ROUTE=FALSE will not meet timing

  - all data associated with a clock must be in the same bank as the clock

     - even adjacent banks (using the MRCC) while architecturally legal results in significantly poorer performance and will not work at higher speeds

 

I have a design that has 9 input clocks, (8 TXCLK clocks coming from each ADC and 1 INCLK for all of the ADC)

Each TXCLK is associated with 4 signals (TXOUT 0,1,2,3) TXCLK samples the data signals TXOUT and load on a shift register the value sampled. (There a 4 shift register per TXCLK).

Than INCLK samples on every rising edge the value of all the shift registers.

I tried to respect the conditions that you enumerated above:

I have put TXCLK 1 2 and 3 in bank A with its associated data

I have put TXCLK 4, 5 and 6 in bank B with its associated data

I have put TXCLK 7 and 8 in bank C with its associated data.

( There weren't enough clock capable pins per bank so i had to seperatge them)

INCLK pin is also in bank C is it a problem that INCLK is going to sample the shift registers of data sampled by clocks in bank A and B?

Here is the figure of the sampling by TXCLK and then by INCLK

schémaechantillonage.png
pinscabale.png
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Explorer
Explorer
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Registered: ‎02-27-2018

Re: Management of clocks coming from an FMC connector to an FPGA

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The maximum rates that i will work at is 25 MHZ for INCLK and 200 Mhz for TXCLK

I will only work in quad lane mode

dual_lane_quad_lane.png
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