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Observer
Observer
4,553 Views
Registered: ‎11-28-2008

PCIe ML507 which GTX ?

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Hello,

 

I'm a bit confused about the location of the GTX transceiver for a PCIe 1x Lane on the ML507-Board.

In the ML507 data sheet the position is given as GTX_X0Y2.

But the ucf-files which where generated by the PCie Core Generator doesn't support this position.

Also Table 5-3 of ug341 (Supported Core Pinouts Virtex5 FXT) doesent't show such a position for a 1x Lane Configuration.

 

Is it critical whish receiver I use for my Pcie design.

 

Thank a lot for your support.

 

Kind regards 

 

Friz

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Xilinx Employee
Xilinx Employee
5,472 Views
Registered: ‎01-03-2008

The PCIe lane is connect to MGT 118_0 on the FX70T-FF1136.  This translates to GTX_DUAL_X0Y2 as the physical site location.

 

If the CoreGen UCF file is incorrect, then you should change the location to match it the PCB implementation.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Xilinx Employee
Xilinx Employee
5,473 Views
Registered: ‎01-03-2008

The PCIe lane is connect to MGT 118_0 on the FX70T-FF1136.  This translates to GTX_DUAL_X0Y2 as the physical site location.

 

If the CoreGen UCF file is incorrect, then you should change the location to match it the PCB implementation.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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Observer
Observer
2,508 Views
Registered: ‎05-14-2014

 Hi, 

 

I am testing GTX pcie protocol over SATA  connector with loop back. Can you specify what changes you made to the origional project. The GTX core never synced up. I am resetting the core from outside. 

 


@mcgett wrote:

The PCIe lane is connect to MGT 118_0 on the FX70T-FF1136.  This translates to GTX_DUAL_X0Y2 as the physical site location.

 

If the CoreGen UCF file is incorrect, then you should change the location to match it the PCB implementation.



@mcgett wrote:

The PCIe lane is connect to MGT 118_0 on the FX70T-FF1136.  This translates to GTX_DUAL_X0Y2 as the physical site location.

 

If the CoreGen UCF file is incorrect, then you should change the location to match it the PCB implementation.





Thanks

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Xilinx Employee
Xilinx Employee
2,506 Views
Registered: ‎01-03-2008

You have responded to a thread that is more than five years old and does not appear to be related to your question. 

 

Based on what I think your question is, you should open a new thread in the PCIe forum with the full details on the problem that you are having.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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