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startnexys3
Observer
Observer
10,193 Views
Registered: ‎04-02-2012

Problem about write and read data from the psram on the Nexys3

Hi experts

I am a  newer in FPGA.Using the Nexys3 board to learn the abc. Recently i try to write a program to communicate with the PSRAM on the Nexys3.I find it is deadly hard to do that,no mater how i modify the code,it doesn't work.I add a UART to send the data to pc and found that  the data i read from the psram that i writed  are all ZERO  ??

Would you please tell me what's wrong with my code?

 

here are my code and the psram' s datasheet.

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15 Replies
eteam00
Instructor
Instructor
10,189 Views
Registered: ‎07-21-2009

Did you simulate your design to verify

  • correct reception by the UART
  • writing correct data to the correct psram address
  • reading correct address from the psram
  • sending correct data by the UART
  • resets and clocks working correctly

You mentioned that you added a UART to the design, but the base design should include a UART.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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startnexys3
Observer
Observer
10,178 Views
Registered: ‎04-02-2012

i count from 0 to 20 and write the number into the ram,then,the next 20 counts,i read from the ram.I have simulated and found that the address bus and timing seems have no question.so i generate the bit directly and program the spartan6.

       I have tested that uart work correctly, i think that the problem may lie in the communication with the ram.I also enable the led to show the data,but all the leds is off,when processing read.

       I read from the datasheet that it access time is both 70ns.so i use the state machine to read and write.i count from 0 to 9 ,when 1,i set the address , give data and pull down the cs and we, when 8, the write is finished.so i pull up the cs and we.read data is similar.

     sense that the nexys3's clk is 100mhz, the write and read time is meetted.so i really don't konw what's wrong.

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eteam00
Instructor
Instructor
10,175 Views
Registered: ‎07-21-2009

If you truly believe that you have done a thorough job of verifying your design with logic simulation, and your design does not function as simulated, then you have few options.  The first option is to verify with an oscilloscope (or ChipScope) that the hardware matches the simulation.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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startnexys3
Observer
Observer
10,171 Views
Registered: ‎04-02-2012

ok  i'll try a chipscope latter.

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startnexys3
Observer
Observer
10,163 Views
Registered: ‎04-02-2012

i try nearly one day to learn to use the chipscope and found that data writen is right, but read is all zero :-(

so i think that the timing must have problem,here is my simulation on writing screen shoot, can you see anyting wrong on it?timming.png

 

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eteam00
Instructor
Instructor
10,160 Views
Registered: ‎07-21-2009

i try nearly one day to learn to use the chipscope and found that data writen is right, but read is all zero

 

Until you can correctly read the data which has been written, you do not know with certainty that the data is correctly written.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Anonymous
Not applicable
10,157 Views

I recently created a Verilog module for the Nexys 3 which successfully does simple PSRAM reads and writes and should be reasonably easy to integrate into another design as long as you don't also need to use the flash chip that shares the same lines. I would be happy to share this with you, except I'm away from home (and my source code) until next Monday. Can you wait until then? FYI- there is a Verilog simulation model that you can use with ISim on the same Micron page as the datasheet, it'll tell you if you've violated important timing parameters or when you've read or written data successfully in the console area. This was extremely useful for me to get my own code working properly. Andy
startnexys3
Observer
Observer
10,151 Views
Registered: ‎04-02-2012

:-)  while waitting for you, I try the FYI first.

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startnexys3
Observer
Observer
10,137 Views
Registered: ‎04-02-2012

:-(  It sense that Micron has stop to provide the FYI  up until now I can't find the simulate model.

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Anonymous
Not applicable
7,712 Views

The sim model is still there.  Go here: http://www.micron.com/parts/psram/cellularram/mt45w8mw16bgx-701-it?pc={BD8A72EA-2DC2-4B88-846E-7B59997A2D97} and click on the Sim Models tab about halfway down the page.

 

In any event, I'm home now, so in the next few minutes I'll look at packaging up my sample code for you.

 

Andy

Anonymous
Not applicable
7,711 Views

OK, here's a ZIP containing a few goodies:

1) The AsyncPSRAM.v module which provides a simple interface to reading/writing the Nexys-3 PSRAM in async mode.  You may need to modify the number of waitstates in the state machine if you use an input clock frequency other than 100Mhz to this module.

2) A module which makes it easy to output values on the seven-segment display (in VHDL, everything else is in Verilog.)

 

Also note that the ISE archiver grabbed the module required for simulating the PSRAM but it claims it won't restore it to the right directory since it was external to the rest of the project.  You should just remove it from the project once you load it in ISE and then re-add it to the project whereever you wind up putting it, if you care about the simulation.

 

If you manage to successfully integrate this with your project, I will be interested to hear what was wrong with the code you tried to write, by comparison. (I would also be happy if someone else is succesful in making use of my code. :-) )


Andy

startnexys3
Observer
Observer
7,702 Views
Registered: ‎04-02-2012

Thanks very much :-)   give me a little time to learn your code, it is quite helpful to me.

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startnexys3
Observer
Observer
7,698 Views
Registered: ‎04-02-2012

 :-) The problem is solved, How ridiculous! All the things about the timing are right. The key lies in Pin constraint. In the sch of nexys3 I found that the data0 of the Psram was connect to another chip the PIC Microcontroller, so I think it couldn't be used for the FPGA, the same is data1 and data 2.so I only connect to the psram with data3..15.

pic.png

after I study the sch carefully I found that data0..2 was also connect to the fpga.So i add the three pins.And  the problem wad solved.All the leds are blinking happly :-)

Here comes my timing and code,maybe these would be helpful to newer of fpga.

write timing:

write.png 

read:

read.png

 

 

By the way,I try to add the verilog psram to my code,but the xst can't Synthesis

it doesn't support real, and can't recognize the word ‘function’ :-(

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Anonymous
Not applicable
7,694 Views

Fyi, the XST verilog compiler supports the verilog "function" keyword just fne, in my experience. Anyway, glad you got your project working.
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Anonymous
Not applicable
6,892 Views

I don't know, if you already made it, but in your simulation, you have OE and WE active (= low) at the same time. For write cycles OE must be high. Otherwise you have a bus contention.

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