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Visitor a_saberi
Visitor
5,052 Views
Registered: ‎11-07-2011

Problem in upsampling and downsampling [Simulink]

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],


  In the paper, I need to implement upsampling and downsampling 

At the first look, it is a peace of cake that should be solved.

Im upsampling/downsalping my signal, but it look unchanged in frequency!!!!!!!

 

Let me describe what I did:

Input: sine soure of 1000Hz wth sampling rate of 1/8192

 

Im doing upsamping and downsaling of 2: The first error was that the system genrator MUST has 1/(2*8192) sampling rate that was solved.

 

the the input is still 1/8192 sampling rate

 

 

but amazingly both upsample and downsampled signal are showing same frequency of 1000Hz

 

Does anybody knows, what could be wrong? in DSP we learnt that the for the upsampled signal the output should has half frequency of the main one and in the case of downsampler it must have double frequecy of the mail one

 

I attached the sink picture here

 

Best

Ali

New Bitmap Image.bmp
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2 Replies
Xilinx Employee
Xilinx Employee
5,045 Views
Registered: ‎11-28-2007

Re: Problem in upsampling and downsampling [Simulink]

First of all, please post DSP and SysGen/Simulink related questions to the DSP Tools board: http://forums.xilinx.com/t5/DSP-Tools/bd-p/DSPTOOL .

 

Up/Down samplings will introduce image or alias, but don't halve or double the signal frequency. I suggest you go back to your DSP book and check how up/down samplings work.

 


@a_saberi wrote:

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],


  In the paper, I need to implement upsampling and downsampling 

At the first look, it is a peace of cake that should be solved.

Im upsampling/downsalping my signal, but it look unchanged in frequency!!!!!!!

 

Let me describe what I did:

Input: sine soure of 1000Hz wth sampling rate of 1/8192

 

Im doing upsamping and downsaling of 2: The first error was that the system genrator MUST has 1/(2*8192) sampling rate that was solved.

 

the the input is still 1/8192 sampling rate

 

 

but amazingly both upsample and downsampled signal are showing same frequency of 1000Hz

 

Does anybody knows, what could be wrong? in DSP we learnt that the for the upsampled signal the output should has half frequency of the main one and in the case of downsampler it must have double frequecy of the mail one

 

I attached the sink picture here

 

Best

Ali




Cheers,
Jim
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Visitor a_saberi
Visitor
5,036 Views
Registered: ‎11-07-2011

Re: Problem in upsampling and downsampling [Simulink]

In you order I will ask it again in that part of fotum but comprese in time domain is equal to stretch in frequency domain and it is a very simple principle:

https://ccrma.stanford.edu/~jos/sasp/Upsampling_Stretch_Operator.html

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