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Adventurer
Adventurer
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Registered: ‎04-25-2017

Programming the ZYNQ UltraScale+ (ZCU102 - Evaluation Board) *NOT* using Block Design

I'm trying to program a Zynq Ultrascale+ ZCU102 Eval Board using systemVerilog only (not block design).

 

I have an SSD connected to the Zynq board, running Linux (LTS 16.04). I'm using Xilinx Vivado to generate and program the bitstream.

After that, I'm trying to do a simple read-write at a particular memory location inside the ZynqCore itself, but when I do that, Ubuntu just hangs.

I'm unable to figure out what I'm doing wrong. Can someone Help?

P.S: I'm fairly new to the Zynq Board and FPGA programming itself.

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