01-02-2013 09:33 AM
I have studied the Zynq-7000 architecture and I discovered the EMIO function:
The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface. This is useful to gain access to more device pins (PL pins) and to allow an I/O peripheral controller to interface to user logic in the PL.
My target is to obtain the Tx-Rx UART signals in the programmable logic to connect to GPIO, standalone of to use the silicon labs USB-TO-UART BRIDGE (don't matter if I use this or not). So, Is there the possibility of to make this connection?
01-02-2013 11:36 AM
I do not believe that the programmable sub system peripheral UART is available to be wired to the EMIO pins: it appears that you only choice is to set these few pins between the processor syste3m, and the logic of the FPGA fabric, as general purpose IO (GPIO) -- in and or out signals.
We have used an additional UART with the AXI interface to add a second UART to the Zync ZC702 PCB, with the RX and TX signals then brought out of the FPGA IO pins to the board's connectors.
Remember you will also need a software driver for this new UART, as well.
Perhaps you could write a software UART using the GPIO pins through the EMIO, but it would not be as fast as a 'real' UART...
01-04-2013 12:00 PM
"I do not believe that the programmable sub system peripheral UART is available to be wired to the EMIO pins"
-I just sent an image from XPS, where the UART1 are enabled to connect with EMIO. What do you think about this?
" it appears that you only choice is to set these few pins between the processor syste3m, and the logic of the FPGA fabric, as general purpose IO (GPIO) -- in and or out signals"
- Can you explain me how can I to make this configuration?
01-04-2013 12:38 PM
EMIO pins, yes,
Extended EMIO pins, no.
So, you may route the UART to EMIO pins. On existing boards, like the ZC702, there are no unused EMIO pins, and no convenient way to get any to use.
I don't know about other boards.
01-07-2013 09:50 AM
I'm think you are confused. I'm referencing to Extended Multiplexed IO (EMIO) and Multiplexed IO (MIO). The Extended EMIO does not exist. So, according with XPS and UG585 user manual, the connection between any UART and EMIO is possible.
What do you think about?
01-07-2013 10:22 AM - edited 01-07-2013 10:25 AM
You may tie the UARTs to the MIO package pins.
But, on the ZC702 PCB, these pins are used for something else, so unless you are going to hack and chop, you can't bring out the second built-in UART core.
There are some GPIO MIO pins brought to the fabric (PL side). I do not believe these are able to be used for the built-in UART.
What document are you referring to in the figure?
01-07-2013 10:29 AM
ah, but on page 34 it seems to say you can do what you want....
But, if it is possible, then why do people tell me it isn't?
A real puzzle now....
01-07-2013 01:52 PM
I have now been told that what you suggest is possible: both, or either uart may be wired to the MIO pins, or through to the EMIO pins, given that there are pins available (there is room for them in the MIO, or PL).
It could be the restriction on the ZC702 pcb is that all of the other EMIO pins are already in use, and there is no more room for the pins....
Of course, you could change the design, remove some EMIO pins, and replace them with the other uart, depending on what you need (or not need).
Good news is that the documentation is correct.
I was being told something that was not true, I apologize for any confusion.
09-22-2014 07:59 AM
if I am right, then I can direct the UART data to the PL through UART0 by using the EMIO
Can someone explain in details how to do so taking into account that I have ZC706 board ??
03-31-2015 01:00 PM
Hi! I was investigating the same question and I found out that connecting EMIO pins and MIO pins is not possible. You can connect the built-in UART transceiver of the Zynq to both EMIO and MIO pins, but you cannot use the MIO pins in the programmable logic (PL) of the Zynq (e.g. to use the onboard UART of the Zedboard in your PL).
Please refer to Zynq's technical reference manual (UG585, p. 385)
The EMIO I/Os are not connected to the MIO I/Os in any way. The EMIO inputs cannot be connected
to the MIO outputs and the MIO inputs cannot be connected to the EMIO outputs. Each bank is
independent and can only be used as software observable/controllable signals.