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Visitor sailorjerry
Visitor
1,004 Views
Registered: ‎08-10-2017

[SP-601] Can I use non differential clock on SMACLK_P pin?

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I'd like to use external 10 MHz clock source instead of on board 27 MHz clock. The external clock I have is not differential though. 

 

I just changed my UCF file from:

 

// ==== 27 MHz clock ====

NET "tcxo_clk_in" LOC = V10; # 27 MHz on board TCXO
TIMESPEC TS_tcxo_clk_in = PERIOD "tcxo_clk_in" 37.037 ns HIGH 50%;

 

to:

 

// ==== 10 MHz clock ====
NET "tcxo_clk_in" LOC = H17; # External 10 MHz clock
TIMESPEC TS_tcxo_clk_in = PERIOD "tcxo_clk_in" 100.000 ns HIGH 50%;

 

 

I also rerun clock wizard to make sure the same system clock as before  is generated.

 

Is there anything else I need to do?  

 

 

 

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1 Solution

Accepted Solutions
1,326 Views
Registered: ‎06-21-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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There are comparators that produce an LVDS output.  You could use something like an ADCMP604 to turn your signal into an LVDS clock and use the port differentially, as it was originally designed.

View solution in original post

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6 Replies
972 Views
Registered: ‎06-21-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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You need to assign "tcxo_clk_in" a single ended IO standard.  Be sure the IO standard matches the signal that you are injecting.  Also, take a look at how the clock is terminated.

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Registered: ‎06-21-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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Also make sure the IO standard can be used with the VCCio on that bank that the clock is on.

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Visitor sailorjerry
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950 Views
Registered: ‎08-10-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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Thanks for a quick response. This is the waveform of my 10 MHz. What IO standard should I use?

fpga-10mhz.png 

fpga-10mhz.png
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922 Views
Registered: ‎06-21-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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Your signal is a sine wave centered around ground.  It goes significantly below 0V.  Unless the SMACLK_P port is AC coupled, you may damage the FPGA.  Is your scope set on 50 ohms input impedance or 1 Mohm?  It makes a difference as to what that signal will look like on your board.  How is the SMPCLK_P port terminated on the board?  That matters too. 

 

In general, sine waves, especially relatively slow sine waves, aren't great for driving clocks.  Since you have a fairly gentle slope instead of a sharp edge, a small amount of noise on the signal translates into significant clock jitter. 

 

It wouldn't surprise me that if the SMA port is AC coupled, that you might find an IO standard that works, but unless you are careful, you are risking the FPGA.  The safe thing to do is to build a circuit with a comparator to translate the sine wave into a logic signal. 

Visitor sailorjerry
Visitor
911 Views
Registered: ‎08-10-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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Thanks a lot, things are getting much clearer now.  Will use the comparator. 

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1,327 Views
Registered: ‎06-21-2017

Re: [SP-601] Can I use non differential clock on SMACLK_P pin?

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There are comparators that produce an LVDS output.  You could use something like an ADCMP604 to turn your signal into an LVDS clock and use the port differentially, as it was originally designed.

View solution in original post

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