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Observer
Observer
5,301 Views
Registered: ‎09-23-2009

SPI ML507 Pins

Hi,

    I'm using the board of ML507.In EDK,I add the core of SPI,but now I have some problem.The errors is that:

   

ERROR:MapLib:30 - LOC constraint P15 on xps_spi_0_MISO is invalid: No such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint N15 on xps_spi_0_SCK is invalid: No such site
   on the device. To bypass this error set the environment variable
   'XIL_MAP_LOCWARN'.

 

    My ucf file is:

 

##SPI
net xps_spi_0_SCK     LOC=N15;
net xps_spi_0_SCK     IOSTANDARD = LVCMOS33  | SLEW=SLOW | DRIVE=6;
net xps_spi_0_MOSI     LOC=AF14;
net xps_spi_0_MOSI     IOSTANDARD = LVCMOS33  | SLEW=SLOW | DRIVE=6;
net xps_spi_0_MISO     LOC=P15;
net xps_spi_0_MISO     IOSTANDARD = LVCMOS33  | SLEW=SLOW | DRIVE=6;
net xps_spi_0_SS<0>     LOC=V9;
net xps_spi_0_SS<0>     IOSTANDARD = LVCMOS33  | SLEW=SLOW | DRIVE=6;

 

What can I do to pass these errors.Thank you!

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Xilinx Employee
Xilinx Employee
5,290 Views
Registered: ‎01-03-2008

Are you sure that you selected a XC5VFX70T-FF1136 device?
------Have you tried typing your question into Google? If not you should before posting.
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Observer
Observer
5,286 Views
Registered: ‎09-23-2009

Yes,i'm sure that i have selected XC5VFX70T-FF1136 device,i don't know how to solve it.
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Xilinx Employee
Xilinx Employee
5,275 Views
Registered: ‎01-03-2008

Check the log and report files to confirm that the right part/package is being used.  Since the N15 and P15 are valid IO locations for the XC5VFX70T-FF1136 you should not be getting this error message.

 

You should also check for other WARNING and ERROR messages that may have occured.

------Have you tried typing your question into Google? If not you should before posting.
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Observer
Observer
5,106 Views
Registered: ‎09-23-2009

Hi,

    I found an answer from the forums,the address is:http://forums.xilinx.com/t5/Virtex-Family-FPGAs/two-questions-about-vertix4-ml405/m-p/70462#M6048,and the spi pins are not as the schematics shows:

Net fpga_0_SPI_FLASH_MISO_pin_m LOC = H33;
Net fpga_0_SPI_FLASH_MOSI_pin_m LOC = H34;
Net fpga_0_SPI_FLASH_SCK_pin_m LOC = G32;
Net fpga_0_SPI_FLASH_SS_pin_m LOC = J32;

They are all GPIO ports,how does it work as spi?Thank you!

enterliu2000

2010.5.21

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Xilinx Employee
Xilinx Employee
5,095 Views
Registered: ‎01-03-2008

Looking through your posts in both threads (please don't double post) you never indicated what device you wanted to connect to SPI and the poster in the other thread had explicitly stated that they had connected the SPI pins to the Expansion Header. 

 

The SPI memory device on the board is intended for use as FPGA configuraiton storage.  It is possible to connect to the memory using these pins

 

SPI_CLK = N15

SPI_SS = V9

SPI_MOSI = AF14

SPI_MISO = P15

 

However, N15 and P15 are special dedicated configuration pins that can only be accessed through the STARTUP_VIRTEX5 primitive.  This is why you had the initial error messages at the beginning of this thread.

 

An application note, XAPP1020, was created that described how to use the STARTUP_VIRTEX5 to be able to access SPI memories that are connected to the configuration port.

http://www.xilinx.com/support/documentation/application_notes/xapp1020.pdf

 

 

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