04-07-2010 12:46 AM
I'm using the board of ML507.In EDK,I add the core of SPI,but now I have some problem.The errors is that:
ERROR:MapLib:30 - LOC constraint P15 on xps_spi_0_MISO is invalid: No such site
My ucf file is:
What can I do to pass these errors.Thank you!
04-07-2010 07:24 PM
04-08-2010 06:47 AM
Check the log and report files to confirm that the right part/package is being used. Since the N15 and P15 are valid IO locations for the XC5VFX70T-FF1136 you should not be getting this error message.
You should also check for other WARNING and ERROR messages that may have occured.
05-21-2010 12:26 AM
I found an answer from the forums,the address is:http://forums.xilinx.com/t5/Virtex-Family-FPGAs/two-questions-about-vertix4-ml405/m-p/70462#M6048,and the spi pins are not as the schematics shows:
Net fpga_0_SPI_FLASH_MISO_pin_m LOC = H33;
Net fpga_0_SPI_FLASH_MOSI_pin_m LOC = H34;
Net fpga_0_SPI_FLASH_SCK_pin_m LOC = G32;
Net fpga_0_SPI_FLASH_SS_pin_m LOC = J32;
They are all GPIO ports,how does it work as spi?Thank you!
05-21-2010 08:39 AM
Looking through your posts in both threads (please don't double post) you never indicated what device you wanted to connect to SPI and the poster in the other thread had explicitly stated that they had connected the SPI pins to the Expansion Header.
The SPI memory device on the board is intended for use as FPGA configuraiton storage. It is possible to connect to the memory using these pins
SPI_CLK = N15
SPI_SS = V9
SPI_MOSI = AF14
SPI_MISO = P15
However, N15 and P15 are special dedicated configuration pins that can only be accessed through the STARTUP_VIRTEX5 primitive. This is why you had the initial error messages at the beginning of this thread.
An application note, XAPP1020, was created that described how to use the STARTUP_VIRTEX5 to be able to access SPI memories that are connected to the configuration port.