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sai_deepthi
Participant
Participant
469 Views
Registered: ‎08-15-2018

SPI Tristate Signals

Hello there!

I'm working on Xilinx SPI IP Core, I'm unable to figure out how to handle tristate signals of IP core. I cannot use SDK and block design as I'm working with external slave SPI device. I can only play with the signals using VHDL/verilog coding.

Do I need to use a tristate buffer in VHDL code for these signals?

Please help me out. Thanks in advance!

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timothyv
Xilinx Employee
Xilinx Employee
424 Views
Registered: ‎07-11-2019

Hello @sai_deepthi 

I have attached links to forum questions that are very similar to the problem you are having. 

I hope this helps, but if it does not, please let me know! 

Forum1: https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Usage-of-tri-state-signals-of-AXISPI-IP-for-use-in-a-3-wire-SPI/td-p/775758

Forum2 (this link is also given in Forum1): https://forums.xilinx.com/t5/Embedded-Processor-System-Design/adc-3-pin-spi/td-p/687805

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