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8,038 Views
Registered: ‎01-30-2014

Simple PCIe (PCI express) endpoint interface to Block RAM Module example or tutorial

I want to generate most basic PCIe core (board is ML605, but it really does not matter), and connect / interface it to Block RAM module on FPGA. No DMA is required: I only want to see how one word of data is written to Block RAM, from PCIe Core's (Endpoint's) interface and what signals are used. I can either generate Block RAM, or just wrie it:


module myRAM( clock, writeEnable, address, data);

    input clock;

    // etc

    reg [DATA_WIDTH-1:0] myBlockRam[ 0:ADDRESS_WIDTH ];

    // etc

endmodule

 

As I understand, TLP packets are used. I studied TLP interface and know it well. Xilinx uses AXI wrappers to interface "User Interfaces" such as DRAM, etc.

Do I need to AXI interface (wrapper) for PCIe's endpoint to interface with simple Block RAM, or can I just use TLP to "User Interface" (such as Block Ram module) directly which is preferred way. Any examples or turorials will be appreciated, too.

It appears that I can just instantiate my own Block RAM module with AXI interface as on page 90 of http://www.xilinx.com/support/documentation/ip_documentation/v6_pcie/v2_5/ug671_V6_IntBlock_PCIe.pdf

FSM inside of my Block RAM module will handle the AXI signaling, TLP encoding/decoding, etc.

How do I then connect my Block RAM module to instantiated PCIe Endpoint (core)?

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Contributor
Contributor
8,018 Views
Registered: ‎05-17-2009

Re: Simple PCIe (PCI express) endpoint interface to Block RAM Module example or tutorial

There's a relatively new app note that might help (XAPP1171), although it only targets Kintex and Zynq.

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