03-19-2018 10:27 AM
VC707 has system LVDS clock - SiTime SiT9102AI-243N25E200.00000. Why board has external termination? That it's possible to set property Diff_Term = True if using IBUFGDS and R166 will not be needed.
03-19-2018 10:37 AM - edited 03-19-2018 10:37 AM
Per the datasheet for the SiTime device,
The 100 ohm at the driver is suggested. The p-p voltage is greater than the LVDS specification, and there is no mention of the driver actually being LVDS compatible. The diffterm on the IBUFG is used.
03-19-2018 01:28 PM
Meeting the LVDS standard is hard,
Easier to not bother, just build a device that has extremely low jitter, and if you follow the data sheet interfaces to different differential standards using a resistor or two.
So, generally, you find a lot of devices (especially clocking) that do some things well (low jitter) but really make no real effort to meet any IO standards.
Not saying they did not consider it. They just didn't do it (create a ANSI or IEEE LVDS standard output). Working with an existing LVDS input is quite easy, if you are allowed to add a resistor to an existing device (it is already close to what is needed).
03-20-2018 02:08 AM
I think the answer is a bit more straight forward.
The SYSCLK connects to bank38 of the FPGA.
This bank is powered at 1.5V
The master XDC file says that the input IOSTANDARD is LVDS.
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
LVDS inputs in a bank with VCCO != 1.8V is allowed but you must provide the termination yourself on the board.