Hello, for one project I need to use a share L2 Cache between a Custom IP and the Zynq 7000. Since the Internal L2 is not accessible through one of the PL ports, I was thinking about using the System Cache IP (which acts as L2 for the microblaze). After making some experiments, I'm not 100% sure that the L2 of the PS is disabled when System Cache is inserted in the PL part. Can anyone confirm me this ?
The PS (ARM cores) have L2. The MicroBlaze may be optioned with caches (not L2 at all, just a cache for data and instructions). So cache in MicroBlaze has nothing to do with the ARM PS.
The PS does have a ACP that is available in the PL. This is an AXI master interface you may put in the PL which is now able to be a third processor (along with the two ARM processor cores) cache coherent so it is able to do anything the other two cores do, including reading and writing L2 cache which is then shared with the 2 cores, and the ACP.