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ksharma3
Visitor
Visitor
10,857 Views
Registered: ‎05-20-2013

Using HDMI port <DIGILENT ATLYS>

Hi,

 

I need information on getting video data using HDMI IN port and storing it in memory.

Also, I am using ISE webpack 14.5. 

 

Thanks,

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS&CFID=186791&CFTOKEN=51420508

 


This zip file contains an EDK demo project that demonstrates using HDMI on the Atlys board. It accepts an HDMI input, buffers the input frames into memory, and then outputs the buffer to another HDMI port.


 

www.xilinx.com
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ksharma3
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Registered: ‎05-20-2013

I did download the project. However,I am using ISE 14.5 and am not sure if I can run the project on ISE .

Also , from what I understand:

 

1) The HDMI IN is a type A connector with 3 pairs of data channels. ( PINS J16 , J18 ; L17,L18 ; K17 , K18 <J3 HDMI IN> )

2) When the source ( say a camcorder ) is connected via an HDMI cable to this port , red , green and blue data bits will be transferred to the HDMI IN . 

3) I just need to store this data in RAM that I can generate using core generator.

4) So , all that I need is kind of an interface verilog file that takes the signals from the pins mentioned in (1) and simply transfers the data to RAM.

 

Is this what actually happens or am I missing anything ? Also which of the .v files given in EDK demo

<Atlys_HDMI_PLB_demo\Atlys_HDMI_PLB_demo\project\pcores\hdmi_in_v1_00_a\hdl>does that?

 

I have just started working on this project and this is the first time I am working with xilinx fpga so it would be great if you could help.

 

Thanks,

 

 

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ksharma3
Visitor
Visitor
10,814 Views
Registered: ‎05-20-2013

Hi,

 

I am trying to "implement" the code given in xapp495 using ISE 14.5. I have included the following files (as I want to get data in from theHDMI port only):

1) dvi_decoder.v

2) phsaligner.v , decode.v , chnlbond.v , serdes_1_to_5_diff_data.v 

Also, I included the file "dvi_demo.ucf" . I need to know what needs to be changed in the dvi_demo.ucf file. IS the following correct:

###########################################
# Setting VCCAUX for different SP601 board
###########################################
CONFIG VCCAUX = 3.3;
#
# Constraint for RX1
#
NET "rxclk" TNM_NET = rxclk;
TIMESPEC TS_rxclk = PERIOD "rxclk" 100 MHz HIGH 50%;

 

PIN "tmdsclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "pclkx2bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "pclkbufg.O" CLOCK_DEDICATED_ROUTE = FALSE;

##################################################
# TMDS pairs for Atlys IN (FPGA Bank 1): J3
##################################################

#HDMI in Ports
NET "tmdsclk_p" LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
NET "tmdsclk_n" LOC = "H18" |IOSTANDARD = TMDS_33 ;
NET "red_p" LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
NET "red_n" LOC = "J18" |IOSTANDARD = TMDS_33 ;
NET "green_p" LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green 
NET "green_n" LOC = "L18" |IOSTANDARD = TMDS_33 ;
NET "blue_p" LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue 
NET "blue_n" LOC = "K18" |IOSTANDARD = TMDS_33 ;

 

Thanks,

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ksharma3
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Registered: ‎05-20-2013

Also, I keep getting the following error. Can anyone please help me with this:

 

ERROR:Place:1205 - This design contains a global buffer instance,
<tmdsclk_bufg>, driving the net, <tmdsclk_OBUF>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: tmdsclk.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.

 

Thanks,

 

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sfortin
Newbie
Newbie
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Registered: ‎06-19-2013

Just add this in the .ucf and it should work fine

PIN "hdmi_in_0/hdmi_in_0/USER_LOGIC_I/Inst_dvi_decoder/pclkbufg.O" CLOCK_DEDICATED_ROUTE = FALSE;

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rpanchal
Newbie
Newbie
10,707 Views
Registered: ‎06-20-2013

Hi,

 

I am new to FPGA and  this foum. I am also  trying to get this demo (Digilent's Atlys HDMI Demonstration Project)  running. I am using ISE webpack 14.5.

 

As ksharma3 has gotten further in the running the Demo application, I would greatly appreciate details of the steps for ISE webpack 14.5. The steps listed in document seems confusing, e.g.. 

4) Create an empty Xilinx C project and a standalone BSP. Copy all files from source\ to the src\ folder in the empty C project. Ensure to overwrite any existing files, and allow the project to build.

 

With ISE14.5 EDK/XPS, the steps seems to be different or I am missing something.

 

I greatly appreciate any help/clarifications on the steps in 14.5.

 

Thanks,

rajpanchal@yahoo.com

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bwiec
Xilinx Employee
Xilinx Employee
10,704 Views
Registered: ‎08-02-2011

The SDK flows have changed slightly over the years. You should refer to the EDK CTT guide for this info:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/edk_ctt.pdf

I'd recommend running through it before tackling this project.
www.xilinx.com
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