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Visitor lalakers1
Visitor
201 Views
Registered: ‎05-23-2019

Using PAD as output and input the same time

Hi Xilinx Applications and FPGA users,

I would like to use HPIOB Pads as output and input at the same time, i.e. Signal Q is driven out to the PAD and the PAD is read as input a tthe same time

Q --> PAD --> cmp1 (Not internal copy of Q  but a connection to PAD IBUF (O).

For Virtex Ultrascale devices , does Xilinx have a way to do this ; make an instance of the pad in RTL, adding I/O components into RTL etc.

Thanks,

 

 

 

 

FYI: This code does not connect to PAD but gives internal copy Q

module flop_iob(input clk,
input D1,
input D2,
input reset,
input sel,
input cmp1,
output compare_test,
inout Q

);

wire user_O;
reg user_o_reg,Q_reg;
reg Q_dly;

assign Q = Q_reg;
assign compare_test = user_o_reg ^ cmp1;

always @(posedge clk)
user_o_reg <= user_O;

always @(posedge clk)
Q_dly <= Q;


always @(posedge clk)
begin
if (sel)
Q_reg <= D1;
else
Q_reg <= D2;
end
IBUF IBUG_LOOP_BACK (.O (user_O),
.I (Q)
);

endmodule

 

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1 Reply
186 Views
Registered: ‎01-22-2015

Re: Using PAD as output and input the same time

@lalakers1 

Welcome to the Xilinx Forum !

There is a way to infer a bidirectional buffer to the IO pad with your RTL, but it is perhaps more straightforward to instantiate the IOBUF primitive into your design as shown on about page 358 of UG974.  When instantiating IOBUF, be sure to include the UNISIM library as also shown on page 358 of UG974.
IOBUFus.jpg

Note that the T-input to IOBUF is used to tri-state (or not) the output portion of IOBUF.  So, you can actually read and write the IO pad simultaneously (although O will equal I).  

Cheers,
Mark

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