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Visitor dankmliu
Visitor
8,724 Views
Registered: ‎09-17-2007

Using RAM on ML505 Board

Greetings,

I have the ML505 Board as part of the Virtex-5 FPGA Gigabit Ethernet Kit.  I have been struggling with how to use the 256 MB DDR2 or the 1 MB ZBT SRAM.  I am pretty new to FPGAs and Xilinx, but I have figured out the basics of working the switches, LEDs, and even the Ethernet MAC.  Now I would like to use the on board memory, but I can't figure it out from the User Guide or any other documentation at the Xilinx site.

If anyone can post some hints or links on how to do this, it would be very appreciated!

Thanks!

-Dan
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3 Replies
Xilinx Employee
Xilinx Employee
8,694 Views
Registered: ‎08-15-2007

Re: Using RAM on ML505 Board

Dan you can use either EDK or MIG.
Here is a link to the reference designs.  Under ML505 Base System Builder and Reference Design Material you will find an EDK based designed that connects to both DDR2 and SRAM (processor based).
Under ML505 Memory Interface Generator Design you will find a design that connects to DDR2 (non-processor based)
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Visitor dankmliu
Visitor
8,675 Views
Registered: ‎09-17-2007

Re: Using RAM on ML505 Board

Chad,

Thanks for the information, somehow I missed that link you posted!  I think this should get me on my way... for now...

-Dan
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Visitor kadeve
Visitor
8,586 Views
Registered: ‎10-17-2007

Re: Using RAM on ML505 Board

One detail: the ml505_mig_design reference design is for the Micron MT4HTF3264HY-53E SODIMM.
My ML505 was shipped with a MT4HTF3264HY-667 SODIMM, and I needed to tweak some parameters.
I'm using:

module mem_interface_top #
  (
   parameter BANK_WIDTH           = 2,       // # of memory bank addr bits
   parameter CKE_WIDTH            = 1,       // # of memory clock enable outputs
   parameter CLK_WIDTH            = 2,       // # of clock outputs
   parameter COL_WIDTH            = 10,       // # of memory column bits
   parameter CS_NUM               = 1,       // # of separate memory chip selects
   parameter CS_WIDTH             = 1,       // # of total memory chip selects
   parameter CS_BITS              = 0,       // set to log2(CS_NUM) (rounded up)
   parameter DM_WIDTH             = 8,       // # of data mask bits
   parameter DQ_WIDTH             = 64,       // # of data width
   parameter DQ_PER_DQS           = 8,       // # of DQ data bits per strobe
   parameter DQS_WIDTH            = 8,       // # of DQS strobes
   parameter DQ_BITS              = 6,       // set to log2(DQS_WIDTH*DQ_PER_DQS)
   parameter DQS_BITS             = 3,       // set to log2(DQS_WIDTH)
   parameter ODT_WIDTH            = 1,       // # of memory on-die term enables
   parameter ROW_WIDTH            = 13,       // # of memory row and # of addr bits
   parameter ADDITIVE_LAT         = 0,       // additive write latency
   parameter BURST_LEN            = 4,       // burst length (in double words)
   parameter BURST_TYPE           = 0,       // burst type (=0 seq; =1 interleaved)
   parameter CAS_LAT              = 3,       // CAS latency
   parameter ECC_ENABLE           = 0,       // enable ECC (=1 enable)
   parameter MULTI_BANK_EN        = 1,       // Keeps multiple banks open. (= 1 enable)
   parameter ODT_TYPE             = 1,       // ODT (=0(none),=1(75),=2(150),=3(50))
   parameter REDUCE_DRV           = 0,       // reduced strength mem I/O (=1 yes)
   parameter REG_ENABLE           = 0,       // registered addr/ctrl (=1 yes)
   parameter TREFI_NS             = 7800,       // auto refresh interval (uS)
   parameter TRAS                 = 40000,       // active->precharge delay
   parameter TRCD                 = 15000,       // active->read/write delay
   parameter TRFC                 = 105000,       // refresh->refresh, refresh->active delay
   parameter TRP                  = 15000,       // precharge->command delay
   parameter TRTP                 = 7500,       // read->precharge delay
   parameter TWR                  = 15000,       // used to determine write->precharge
   parameter TWTR                 = 10000,       // write->read delay
   parameter IDEL_HIGH_PERF       = "TRUE",       // # initial # taps for DQ IDELAY
   parameter SIM_ONLY             = 0,       // = 1 to skip SDRAM power up delay
   parameter CLK_PERIOD           = 5000,       // Core/Memory clock period (in ps)
   parameter RST_ACT_LOW          = 1,       // =1 for active low reset, =0 for active high
   parameter DLL_FREQ_MODE        = "HIGH"        // DCM Frequency range
   )


This is for operation at 200 MHz.

regards,
koen


Message Edited by kadeve on 10-23-2007 01:21 AM
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