I'm trying to port a high-speed ADC reference design to the VC707 board. The ADC sits on an FMC module and therefore connects to the FPGA via the FMC pins HA_P/N, HB_P/N and LA_P/N. I've encountered a timing error and on investigation discovered a bizarre problem with this board. The attached picture shows the HA pins (in red), the HB pins (in yellow) and the LA pins (in blue). As you can see the HA and HB pins a grouped respectively whilst the LA pins are split between two locations in nearly opposite corners of the device. This results in the logic connecting to the LA pins being placed roughly in the mid point of the pins which isn't helping with my timing problem. I could add some registers but thought i'd try and determine if this pinout for the LA pins is correct as it just seems wrong to me. Can anyone help?
I got the pin information from the VC707 master UCF and am currently checking through it with the VC707 user guide.