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gonen
Visitor
Visitor
8,762 Views
Registered: ‎12-11-2013

VC707 non responsive after iMPACT programming - Self test required

Hi,

I'm a xilinx EVK veteran but I'm getting a really puzzling problem.

 

Re-configuring my VC707 with an already functioning bit file, the design stops responding and it seems no clock is generated.

Disconnecting all cards (4DSP FMC116) and cables and after a new power cycle I'm not able to configure any version.

 

iMPACT identifies JTAG chain correctly, programs the FPGA successfully - but design is unresponsive.
Even a blinking led is not working.

 

Running through the steps at "AR# 51233 - Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist:
http://www.xilinx.com/support/answers/51233.html

All voltage leds seems are on and GPIO leds are blinking on after the other.

 

Still, trying to test using the VIVADO BIST for VC707 failed on loading design
(https://secure.xilinx.com/webreg/clickthrough.do?cid=389658&license=RefDesLicense&filename=xtp205-vc707-bist-c-2015-1.pdf&languageID=1)
Vivado tcl log :

 

****** Vivado v2015.2.1 (64-bit)
  **** SW Build 1302555 on Wed Aug  5 13:06:02 MDT 2015
  **** IP Build 1291990 on Mon Jul 27 03:18:52 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

Vivado% cd C:/vc707_bist/ready_for_download
Vivado% source bist_download.tcl
# open_hw
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2015.2
  **** Build date : Aug  5 2015-13:32:20
    ** Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.


# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]

# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/
210203A02379A
# set_property PROGRAM.FILE {bist_app.bit} [lindex [get_hw_devices] 0]
# current_hw_device [lindex [get_hw_devices] 0]
# refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7vx485t (JTAG device index = 0) is programmed
with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Cha
in 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free runni
ng clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN sca
n_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determ
ine the user scan chain setting, open the implemented design and use: get_proper
ty C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
# program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB):
 peak = 400.465 ; gain = 0.000
# refresh_hw_device [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1434] Device xc7vx485t (JTAG device index = 0) is programmed
with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Cha
in 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free runni
ng clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN sca
n_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determ
ine the user scan chain setting, open the implemented design and use: get_proper
ty C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
# disconnect_hw_server localhost:3121
# close_hw
Vivado%




 

 

 

This happens with 2 boards already, mid work, with working bit files.

 

Any help is appreciated

 

Gonen

 

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3 Replies
venkata
Moderator
Moderator
8,743 Views
Registered: ‎02-16-2010

Check the clock connected to debug hub in your design.
Try changing this clock source to confirm if the earlier clock source has some problem on the board.
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gonen
Visitor
Visitor
8,740 Views
Registered: ‎12-11-2013

Thanks a lot for the prompt response.

 

How do I actually "Check the clock connected to debug hub"?

Is ther a simple walkthroug on how to check/modify it?

 

Thing is, my setup eas working perfectly fine with similar bit file.

 

What can be the cause of such malfunction?

I'm not even sure WHAT is wrong...

 

Thnaks again...

Gonen

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smarell
Community Manager
Community Manager
8,717 Views
Registered: ‎07-23-2012

Open the implemented design and see if you have assigned the clock to the correct pin or not. In case if you generate the clock through a MMCM/PLL, monitor the LOCK signal on a LED.
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