05-14-2012 03:42 AM
Have anyone succeeded in implementing ethernet (using AXI4-stream FIFO) on the VC707? I am using 13.4 and did soon realized that the tool doesn't give me the same support as it do for the ML605 board. I can not create a template design with ethernet.
There is not any example design source code available from xilinx either. Only a bit-file with a readme that says that I should look into another design (the BIST with its document xtp140.pdf) for ethernet source code. But in this document (or design files) there is no ethernet source or information.
However, I have made a manual design using ISE/EDK/SDK and created a peripherial test projet. The thing start but freezes when the the ethernet/FIFO-combo is taken out of reset. As far as I understand, the ethernet core does not start.
09-14-2012 03:20 AM
we're also trying to implement the 1GbE interface in the VC707.
We tested the Xilinx provided bitfile, everything is fine. But as you say: there is no source code to verify...
As we had designs making use of the tri-mode-ethernet (running 1GbE) on ML507 and ML605 using gmii with the Xilinx core for us was doable.
Now on VC707 everything seems to be different.
Currently we're trying to set up the 1000BASE-X PCS/PMA core, using the SGMII interface.
Simulations of that core design at 1Gbit fail, 100Mbit seems to work.
Can anybody explain? Does anyone have any experience or the same problems?
Best regards, Steffen
10-16-2012 09:08 AM
Has anyone had any luck with this issue?
I am using the BIST ISE 14.2 example design for the VC707. I had to connect the 'GTX_CLK' signal of the axi_ethernet module to bring the PHY out of reset. But the TX LED on the PHY is not active.
When I use an axi chipscope monitor on the receive axi streams from the ethernet controller to the axi dma, the resets are not active. However, when I try to ping the FPGA, none of these signals change value. I am assuming the axi ethernet controller is still in reset for some reason or a clock is not being provided properly.
11-04-2012 06:12 PM
I am also trying to get an SGMII core to work on the VC707 board with a MicroBlaze design. I noticed the BIST design has an ethernet core, but there are no sample applications for it. Has anyone had any success integrating SGMII with a MicroBlaze system and using the SDK to run something like their Light Weight IP (LwIP) or transfering data to the FPGA via Ethernet?
12-05-2012 01:53 PM
How did you find the ucf file for VC707? Also in the manual it is not mentioned where the pins like PHY_DRX....and PHY_DTX ...and PHY_COL should be connected! Do you know how to handle that? I am using XPS 14.3!
Please let us know what's the solution for this!
Where can I find a working ucf for Ethernet?
12-22-2012 09:57 AM
12-22-2012 10:02 AM
lamiastella: The ucf file is included in the documentation supplied with the VC707 card. The signals you refer to is related to the GMII interface (I think) which is not used by the card. I think this is the reason these signals are not included in the UCF (if they are left out, I mean. I haven't checked.)
A full schematics for the board (a pdf) is also supplied and any signals that may be missing in the UCF could be found there. However, I would bet that the GMII-specific signals is not available on the card.
12-27-2012 07:01 AM
I have been working on this issue for about 3 weeks. My observation is that axi_ethernet with SGMII interface somehow does not activate the mgts even though from the status registers it says that MGT's are ready and everything is well met for the transmission.
I have been trying with ISE ver 14.4 but still no response to the lwip echo server application. All the initilizations speed settings are well done but what I saw is that the gratious ARP from the board does not come out from the PHY as I am monitoring through the Wireshark. This I guess again is related to the Axi_ethernet IP with SGMII interface configuration.
Hope Xilinx can find a quick fix for this.
01-02-2013 01:43 AM
I have tried the a design that Xilinx claims work on Rev B of the VC707. The design consists of a pre-build bit-file and two SDK projects. One is a peripherial test and the other is a (pingable) Echo server. I can not make this work on my card, however. I have tried to do a design using 14.4 and get the same result.
In all cases the SDK projects fail at the same function. It is during intitilization of the Axi Ethernet the MAC IP does not seem to leave reset and after a timeout an assert is failing.
Will post more if I have some progress.
01-09-2013 10:25 PM
I am still at the same point no progress regarding to the axi_ethernet with SGMII and with Microblaze. However I have managed to get a communication done with pure FPGA logic using tri_mac_ethernet core and gig_eth_pcs_pma core on VC707 and on my custom design board. This proves that the hardware is correct for SGMII communication. However for functional use I have to run TCP/IP, and for that I have to run lwIP with the AXI_ethernet which is the case that I am stuck in.
Will post if I have any progress.
01-13-2013 12:41 PM
I'm in the same boat. I need the lwIP example running to prove connectivity and have also experimented with my own MHS wiring based on the KC705 board base system but to no avail. The VC707 uses a new serial chip rather than an 8-bit GMII interface like the other Xilinx dev boards and my belief is that there is some configuration issue in setting up the transceivers for SGMII functionality. Or, it might be communication between the tri-mode MAC and the transceiver that's not working correctly. As of ISE 14.4, Xilinx still does not support a base system build including ANY ethernet interface.
What I don't understand is how they can send out working bit files but no MHS/UCF files so we can duplicate this ourselves. What good is their working bit file if we can't build our own system around their working example? Why won't Xilinx release the source files for the working bit files they have available?
01-18-2013 03:58 AM
Are you aware of (Xilinx Answer 46384): http://www.xilinx.com/support/answers/46384.htm?
01-21-2013 12:43 AM
I am aware of this solution but it seems to be a solution for ethernet interface without Microblaze. When axi_ethernet is used as it is a licensed core, there is no access to the source files which implies that we cannot apply the same solution to this particular case.
01-28-2013 04:46 AM
I am working with AXI Ethernet in 1000MBit Soft TEMAC SGMII mode on VC707 board and got some partial success. I connect the AXI Ethernet to AXI DMA and use it alongside a Microblaze with Linux running on it.
When I disable AN, I notice that I can send packets correctly, but reception does not work well: Most of the received frames are dropped by AXI ethernet internally and the packets that come through have some bit errors.
When disabling dropping of bad frames, all received frames come through but have even more bit errors, alongside with wrong packet lengths.
That the frames are dropped inside AXI Ethernet already suggests that the problem lies in between PHY and AXI Ethernet, but not within the AXI streams or DMA.
I already tried the same setup on different boards, with different cables and different ethernet devices on the other side of the link, so that I can exclude faulty hardware.
Am I missing something? Maybe some additional constraints? Has someone got to a similar problem? Or has anyone already got a working setup for AXI Ethernet on VC707 board?
Thanks in advance!
01-30-2013 07:02 AM
02-12-2013 05:18 AM
I have come to solution where I have succesfully get the axi_ethernet working in SGMII mode with Microblaze.
I have been in contact with Xilinx for about a month and at last we have come to an solution.
The solution is that you have to update the axi_ethernet core and the lwip drivers with the Xilinx patched ones.
After that by using these core and driver by putting them in the repository, compile all the design again and finally you will get a working ethernet with lwip in SGMII mode.
I am sending out the patches below named as reporsitory. This includes lwip drivers and axi_ethernet core.
I hope this will fix it for you.
02-19-2013 03:31 PM
Thanks for the post Berk. I'm a little new to this and having some issues with the proper connections to the IP. Could you share the relavent parts of your mhs so I can see how you connected everything?
02-19-2013 06:07 PM
Thanks for the post Berk. Any comment about the Config 4 pin? According to the datasheet of MAX88E1111, this pin shouldn't be left float. But in VC707 board it does. The status of Config 4 pin doesn't matter?
02-20-2013 01:33 PM
I added an axi_dma to connect to the axi_ethernet and was able to build the system. But I ran into trouble when I tried to use lwip; the program would hang at lwip_sock_init.
02-21-2013 07:44 AM
02-21-2013 08:04 AM
I took Xilinx BIST example for ISE 14.1. It has right architecture of microprocessor system (axi_ethernet and dma instantation - what you asks). Changed it to SGMII. This project has error in clock_generator, correct it.
So I updated cores and lwip with Berk's files, created LwIp application and corrected it with raw example from xapp1026. It works.
Try this way!
03-04-2013 08:12 AM
For those interested in getting axi_ethernet working alongside with Linux, I have just worked it out.
I also had the same problems with the inconsistent outputs of the PHY registers that return 0 (0x2 and 0x3) and 1 (0x4). But even if the read values are wrong, writing to those registers has an effect.
I haven't bothered with using the Marvell PHY driver, but put some dirty hacks into the generic one.
For reference, I attach my MHS file, as well as the modified versions of xilinx_axienet_main.c and phy_device.c.
PS: If it still does not work, you should look for some application to test whether the ethernet hardware is actually working correctly. I have spent almost 2 months working on a broken board (rx was broken), as the Xilinx Ethernet reference design is no use for verifying correct functionality.
03-15-2013 07:19 AM
just wanted to let you know my findings on this vc707 + axi_ethernet issue since my last post (email@example.com).
Please note, that I did not follow this thread in last weeks and so I didn't have a chance to test/try berkbasaklar and
03-26-2013 01:13 AM
Quite the same for me here. I build my system using C_PHYADDR = 1 as my physical PHY address is 7. Now, I can read/write both PHY correctly.
BUT reseting the isolate bit has no effect. Effectively, the link status bit (internal PHY reg 1 bit 2) sometimes is 1, sometime 0.
Is it possible to do a loopback like : RJ45-> ext PHY -> int PHY-> ext PHY -> RJ45 to validate communication between FPGA and ext PHY ?
04-08-2013 08:09 AM
Hi , thanks for the files you uploaded. Can you help me also with the UCF file? As someone already said before, the UCF file produced by ISE for the VC707 board doesn't contain the LOC assignments for the Ethernet plug.
Did you get (or write) a working UCF with such assignments?
04-10-2013 02:13 PM
Check out page 37 of the VC707 user guide for the pin locations. It doesn't list the I/O standards, though, but I'm sure you can figure out an appropriate choice from the Marvell documentation. These assignments are in the master UCF file, but you do need to go digging through for the proper names, which are not the same as the default names generated in XPS.
04-11-2013 03:12 AM
From the VC707 manual I can see that the data buses (both rx and tx) between the FPGA and the Marvell device are serial differential lines, even if the remaining connections are ethernet signals. In EDK there is no Ethernet IP managing a serial connection with a PHY device. The only IPs I can find between the standard repository are:
- AXI Ethernet embedded IP v.3.01.a (two 8-bit data buses for rx and tx data)
- AXI 10/100 Ethernet MAC Lite v.1.01.a (two 4-bit data buses for rx and tx data)
There isn't any other Ethernet MAC controller I can use...
Moreover, if I wanted to create a custom EDK IP to manage the communication between FPGA and the Marvell device I would need at least the communication protocol technical specification (but it would be much more better the Marvell PHY device manual). Unfortunately such manual is not available online, on the Marvell website. You can download only the "product brief" pdf, that is a poor documentation, of course (here it is the link).
I opened a webcase, let's see what will happen...