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Visitor llopacinski
Visitor
13,844 Views
Registered: ‎06-12-2014

VC709 clock for 10G Ethernet SFP

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Hi,

 

 

I am trying to run 10G Ethernet on the VC709 board, but I have no results since a few days. Probably I have problem with a clock. I will describe my way of thinning and I would like to please anyone of you to correct me. There is no any easy example for the board, what demonstrates a usage of the SFP transceivers (as far I know).

 

1. I think, there is no any possibility to connect the onboard 156,25 MHz clock generator directly to the SFP quad (the pins are connected to a different clock regions).

 

2. To connect the required clock reference for the 10G Ip-core, I need to use the onboard SI570 programmable oscillator. The oscillator is connected to pins AK34 and AL34 (the oscillator has differential output).

3. I need to route the pins AK34 and AL34 (the 156,25MHz oscillator) to pins AW32 and AW33 (input to the jitter attenuator Si5324). Here I have the first problem, the Vivado do not recognizes the pins pair AK34, AL34 and AW32, AW33 like a differential pairs. Because of this I am routing it like a two not related signals. Is this correct? In VHDL I'm doing it like this:

 

 clk_156_MHz_out_p <= clk_156_MHz_in_p;  

clk_156_MHz_out_n <= clk_156_MHz_in_n;

 

(I also do not know the I/O standard??? LVCMOS18?  STL_15_DCI???)

 

Should it be done like this, or somehow via constraints? I know that I should use BUFG for  them, but why fpga is not detecting it like a differential input buffers? Makes my routing any sense?

 

4. After the jitter attenuator Si5324 I can get my 156,25 MHz clk on pins AH8 and AH7 (vivado detects it like a differential buffer and that is correct). The location is ok - it belongs to the SFP quad.

 

5. From AH8 and AH7 I connect the pins to the “Ten Gigabit Ethernet PCS/PMA 10GBase-R” IP core to   refclk_p   and refclk_n inputs.

 

6. After this I expect that I can use core_clk156_out output of the IP core for my design. For example I implemented simple counter to get a "heartbeat" of the clock, but the counter is not counting at all, so I assume there is no clock.

7. Requires the 156MHz clock generator (Si570) any configuration procedure after power on? (In VC709 is written that it is working immediately with 156,25MHz)

 

8. Requires the jitter-attenuator Si5324 any start up configuration after power on ? (it is not explained in the VC709 user guide, so I assumed that it is working immediately after power on and I do not have to control it from the fpga logic)

 

9. And the last question, I really do not understand how the v7_xt_conn_trd design from Xilinx can operate with the SFP ports (connectivity example). I could not find any clock routing from the Si570 to the Si5324... they just are using AH7 and AH8 pins and it works (how?). I also see some initialization on I2C bus, but I do not know what kind of magic is there. It is not explained in any pdf. I am too stupid to understand it, or I am blind and a can not find it.

I am a student on a university, so my work is related to non-profit project. Before I was using only some very old low-end fpgas, and there was no any problems with clocking at all. This VC709 board is a little bit crazy for me.

My last idea is to try some external 156,25 MHz generator, but I do not have it. In my case there can be probably two possibilities, or my fpga do not get any clock because of Si5324 or Si570; or the design is wrong synthesized and the PLL in IP core is not starting up.

Best regards

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1 Solution

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Xilinx Employee
Xilinx Employee
21,999 Views
Registered: ‎01-03-2008

Re: VC709 clock for 10G Ethernet SFP

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1) That is right the SI570 does not have any connections the the MGT reference clocks on the VC709

 

2) You should not use the SI570 for the 10G core, you should be using the SI5324 which is connected to the MGT reference clocks in the same quad as the SFP+ interfaces.

 

3) No, this is not the connection that you want to make.  The AW32/AW33 are for connecting a recovered clock from the MGT to the SI5324 after the CDR has locked for synchronous operation. You must instantiate an IBUFDS for differential inputs and an OBUFDS for differential outputs, connecting them as you described would not work.

 

4) Yes, AH8/AH7 are the pin locations for the MGT reference clock.

 

5) Yes.

 

6) No.  You must first configure the SI5324 using I2C to use the free running mode to start up as 156.25 MHz.  Without being configured the SI5324 does not produce any output.

 

7) The SI570 does not require any I2C programming to start with the default frequency of 156.25 MHz.

 

8) Yes, the SI5324 must be configured.

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10 Replies
Xilinx Employee
Xilinx Employee
22,000 Views
Registered: ‎01-03-2008

Re: VC709 clock for 10G Ethernet SFP

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1) That is right the SI570 does not have any connections the the MGT reference clocks on the VC709

 

2) You should not use the SI570 for the 10G core, you should be using the SI5324 which is connected to the MGT reference clocks in the same quad as the SFP+ interfaces.

 

3) No, this is not the connection that you want to make.  The AW32/AW33 are for connecting a recovered clock from the MGT to the SI5324 after the CDR has locked for synchronous operation. You must instantiate an IBUFDS for differential inputs and an OBUFDS for differential outputs, connecting them as you described would not work.

 

4) Yes, AH8/AH7 are the pin locations for the MGT reference clock.

 

5) Yes.

 

6) No.  You must first configure the SI5324 using I2C to use the free running mode to start up as 156.25 MHz.  Without being configured the SI5324 does not produce any output.

 

7) The SI570 does not require any I2C programming to start with the default frequency of 156.25 MHz.

 

8) Yes, the SI5324 must be configured.

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Visitor llopacinski
Visitor
13,822 Views
Registered: ‎06-12-2014

Re: VC709 clock for 10G Ethernet SFP

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You are right. Now I have implemented your tips and the clock is ticking.

BTW: now I have found the solution described by you on page 52 in ug962. I am sorry that I missed that info. I was searching for configuration of Si570 instead of Si5324.

I would like to ask you another question. I know that the example connectivity design do not use any feedback to the Si5324 (pins AW32/AW33), but it is written in user guide that that pins can be used for clock recovery. Does it mean that I can connect the output of the 10G PMA/PCS core (core_clk156_out) to AW32/AW33 pins or something else? What can be connected to the AW32/AW33 pins?

Thank you for the replay, the answer was very helpful for me and I am sorry that I missed that point in ug962.
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Xilinx Employee
Xilinx Employee
13,811 Views
Registered: ‎01-03-2008

Re: VC709 clock for 10G Ethernet SFP

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Sending the recovered clock to the Si5324 is only required for a synchronous system such as an implementation of Synchronous Ethenet (SyncE) or SONET.  The example design doesn't have this feature so the connection is not used.

 

If you were to use this feature then the design must use the receiver's recovered clock from the MGT and connect this to the AW32/AW33 pins.  The SI5324 also needs to be configured to switch from the free running mode to the CLKIN1 input and this should be done only after the CDR has locked.

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Observer almehdi
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13,670 Views
Registered: ‎03-18-2014

Re: VC709 clock for 10G Ethernet SFP

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Hi,
Can you please explain how to make the Si5324 work ? As you have said there is no output and i didn't really unterstand how to make it work with I2C ?
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Xilinx Employee
Xilinx Employee
13,658 Views
Registered: ‎01-03-2008

Re: VC709 clock for 10G Ethernet SFP

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There is a tutorial and example design for the VC709 that explains how to set the Si5324.  You can find it here:

http://www.xilinx.com/vc709 -> Docs & Designs -> Latest Docs & Example Designs -> Documentation -> 201x.x (select the tool verson that you are using) -> Example Designs -> XTP241

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Observer almehdi
Observer
13,622 Views
Registered: ‎03-18-2014

Re: VC709 clock for 10G Ethernet SFP

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Is it possible to activate si5324 in C code without using interrupt as it is done in the example design ? If it is the case is there an example of a C code making it work this way ?

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Xilinx Employee
Xilinx Employee
13,614 Views
Registered: ‎01-03-2008

Re: VC709 clock for 10G Ethernet SFP

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The sources are available with the XTP and you can make any necessary modifications to meet your needs.

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Visitor sebwerner
Visitor
13,426 Views
Registered: ‎07-21-2014

Re: VC709 clock for 10G Ethernet SFP

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Hello everyone,

 

your discussion was very helpful. I checked the user guides and XTP example designs you proposed, however, i'm still not certain about how to create the 156.25Mhz clock to the pins AH7/AH8 with Picoblaze and the SI5324 module. I there anywhere an example .xdc about how to connect the necessary ports to my design ? ALso, is there a guide on how to programm the SI5324 with picoblaze? And how do i integrate picoblaze into my design?

 

I can't really find any information about that in any user guide or reference design. Would it be possible for someone to maybe share an example -xdc file here? 

 

Best wishes,

Sebastian

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Visitor llopacinski
Visitor
12,154 Views
Registered: ‎06-12-2014

Re: VC709 clock for 10G Ethernet SFP

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FYI:

 

the picoblaze for 156,25 MHz clk setting can be taken from the VC709 reference design.

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Newbie chenyifan
Newbie
6,515 Views
Registered: ‎12-10-2012

Re: VC709 clock for 10G Ethernet SFP

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Could you tell me how to realize 10G Ethernet on the VC709 board?

Thanks

 

 

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