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Observer wangxiao@skhms
Observer
482 Views
Registered: ‎10-30-2018

VCU128 EVB FPGA GTY to FMC+ connection has poor PCB layout design

When designing the daughter card plugged on VCU128 EVB FMC+ connector, It is found from the VCU128 PCB layout file, vcu128-gerber-files-rdf0500.zip, that the FPGA GTY differential signal pairs connected to FMC+ connector has large trace length mismatch (about > 40-70 mils) between the two traces in each differential pairs. For example, the trace length for FMCP_HSPC_DP1_M2C_P is 3406.597mil and for FMCP_HSPC_DP1_M2C_N is 3330.485mil, the length mismatch is about 76.112mil. Which is very bad to run these GTY<->FMC+ connection at high rate >16Gbps. I wonder if Xilinx has tested GTY signals on the VCU128 FMC+ connector or not??  If Xiinx see any issue in testing these GTY<->FMC+ connection??   (We are using the VCU108 EVB too, which has good PCB layout for the GTH output traces to the FMC connector, and does not have the same issue.)

Also we would like to know what is the PCB trace impedance designed for these GTY to FMC+ differential pairs. It is documented that the impedance for the trace between VCU128 PCIe EP edge connector and the FPGA GTY is 85 ohms, but not clear for the trace impedance from FPGA GTY to FMC+?

Thanks

Xiao

 

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4 Replies
Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎06-21-2018

Re: VCU128 EVB FPGA GTY to FMC+ connection has poor PCB layout design

Hi Xiao,

Here are the guidelines for the PCB design:
https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

At first glance, I couldn't find any violation on those traces.

In the vcu128-allegro-board-xtp537.zip you can find the stackup details that are available.

Thanks,
Andres

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Observer wangxiao@skhms
Observer
419 Views
Registered: ‎10-30-2018

Re: VCU128 EVB FPGA GTY to FMC+ connection has poor PCB layout design

Hi Andres,

I could not see any PCB design constraints in this user guide for the GTY differential pair trace layout. Refer to the industrial standard spec for PCIe interface (Gen3 and Gen4), the differential pair trace length mismatch should be < 5~10mils. VCU128 PCIe to GTY connection meets this requirement, but we do not see the same design constraints is used on the GTY connection on the FMC+ side, which gives users difficulties to do PCIe interface design on the FMC+.

My question still is that if Xilinx lab has tested the GTY signals on the VCU128 FMC+ or not?? Is it working if we do differential pair trace length conpensation on the FMC+ daughter card layout??

Thanks,
Xiao

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Observer wangxiao@skhms
Observer
291 Views
Registered: ‎10-30-2018

Re: VCU128 EVB FPGA GTY to FMC+ connection has poor PCB layout design

The VCU128 is the only available PCIe Gen4 EVB, but its FMC+ PCB routing is badly designed for running PCIe Gen4 connection. I had tried to run PCIe Gen4 X4 RP IP test on VCU128 FMC+, and failed in the initial Gen4 rate link up test in our lab. The chipscope shows that the 130b/128b decodering signals on RX GTY output port goes wrong frequently, especially on the GTY RX lane#1. I believe that it is caused by the poor PCB layout at the FMC+ connector which I reported before. If we check the FMC+ DP#1 differential pair (PCIE lane#1 in out design) routing more, we found that the differential pair traces for the lane#1 is badly routed in non-differential way, see attached picture captured from VCU128 board design file. I do not think the FMC+ GTY differential trace can work at high rate (>16 Gbps) on these kind of routing.

The GTY differental pair trace layout on the PCIe EP port is well routed on VCU128 board, but the designer does not apply the same routing design to the FMC+ side.

I still do not see the answer if Xilinx has tested FMC+ differetnial pair signals in their lab or not?

VCU128 FMC+ diff-pair trace.jpg
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Newbie azuremind78
Newbie
257 Views
Registered: ‎09-25-2019

Re: VCU128 EVB FPGA GTY to FMC+ connection has poor PCB layout design

Xilinx support:

Please refer to the attached pdf file for detailed issue description.

Thanks.

 

Xiaofang Chen on behave of Xiao Wang

SK hynix

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