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Visitor ppereira
Registered: ‎09-18-2018

Variable frequency clock (constraints)

Hi There,

I am working on a project that uses 2 IPs (Clock Generator) - one to generate the control clock (10MHz) and the other to generate the work clock (200MHz), both from the same source 100MHz (available on board). I'm using two different IPs, because I want to be able to change the work clock frequency on-the-fly via DRP (Dynamic Reconfiguration Port) of the work clock (from 10MHz to 200MHz).

My questions are:

- I want both clocks (10 and 200) to be phase aligned. How can I set that constraint?

- I want to specify a start frequency of 10MHz (for the work clock - 200MHz max). How can I specify a global constraint so that the design "knows" that despite the frequency (initial) is 10MHz, the placement and routing, should be done as if I was using the max frequency (200MHz).

Best Regards,

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