I am using Virtex 5 Embedded Ethernet HW MAC IP Core on a ML506 Board. The example-code uses the given 12.5 MHz clock from mac to access the data.
For my other logic I use a 100 MHz clock from another source. Now I have to clock out each bit of every byte received over ethernet (serializing). But as 100 MHz clk and 12.5 MHz clk are not derived from each other, they have no constant divider between them. Ond therefore I get bit-flips sometimes. Same problem with sending data. Is there a possibility to clock the HW MAC with my own 12.5 MHz, derived from the 100 MHz clk?
Or are there other possibilities to solve this problem?