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Visitor kisel.93
Visitor
525 Views
Registered: ‎02-19-2018

Vivado does not assign right pins when using my custom board.xml

Hi,

 

I am trying to create a board.xml file for my custom board based on xcku115. I've created project using DDR3 controller and PCIe-DMA via selecting board interfaces. Also added MicroBlaze and GPIO. I have 2 strange issues:

 

All DDR3 intrface pins are assigned correctly except the DM pins, they remain unassigned. I used kcu1500 board file as template for creating mine.

interface definition in board.xml:

<port_map logical_port="DM" physical_port="c0_ddr3_dm" dir="out" left="7" right="0">
              <pin_maps>
                <pin_map port_index="0" component_pin="c0_ddr3_dm0"/>
                <pin_map port_index="1" component_pin="c0_ddr3_dm1"/>
                <pin_map port_index="2" component_pin="c0_ddr3_dm2"/>
                <pin_map port_index="3" component_pin="c0_ddr3_dm3"/>
                <pin_map port_index="4" component_pin="c0_ddr3_dm4"/>
                <pin_map port_index="5" component_pin="c0_ddr3_dm5"/>
                <pin_map port_index="6" component_pin="c0_ddr3_dm6"/>
                <pin_map port_index="7" component_pin="c0_ddr3_dm7"/>
              </pin_maps>
            </port_map>

Interface is written in accordance to C:\Xilinx\Vivado\2017.4\data\ip\interfaces\ddrx_v1_0\ddrx_rtl.xml

pin assignments in part0_pins.xml

    <pin index="126" name ="c0_ddr3_dm0"        loc="G35"/>
    <pin index="127" name ="c0_ddr3_dm1"        loc="K36"/>
    <pin index="128" name ="c0_ddr3_dm2"        loc="E36"/>
    <pin index="129" name ="c0_ddr3_dm3"        loc="F38"/>
    <pin index="130" name ="c0_ddr3_dm4"        loc="H27"/>
    <pin index="131" name ="c0_ddr3_dm5"        loc="M25"/>
    <pin index="132" name ="c0_ddr3_dm6"        loc="D28"/>
    <pin index="133" name ="c0_ddr3_dm7"        loc="B30"/>

In ddr3_0_1_board.xdc file there are all pins except DM.

 

The second problem is that there are 3 gpio pins created in block design instead of 10 and synthesis throws some critical warnings:

CRITICAL WARNING: [Constraints 18-631] No BOARD_PART_PIN found named 'GPIO_LED_0'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:3]
CRITICAL WARNING: [Constraints 18-631] No BOARD_PART_PIN found named 'GPIO_LED_1'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:5]
CRITICAL WARNING: [Constraints 18-631] No BOARD_PART_PIN found named 'GPIO_LED_2'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:7]
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:9]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:11]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:13]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:15]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:17]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:19]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.
CRITICAL WARNING: [Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. [c:/FPGA_projects/simpleDMA_board/simpleDMA.srcs/sources_1/bd/simpleDMA/ip/simpleDMA_axi_gpio_0_0/simpleDMA_axi_gpio_0_0_board.xdc:21]
Resolution: Modify the set_property command to apply the property on the correct object type. Since the property is being applied as a scoped constraint, ensure the proper connectivity of the object port objects can be translated into pin objects. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced.

I attached all board files and auto-generated xdc for ip pinout definitions. Tried to use Vivado 17.2 and 17.4

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