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Anonymous
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XPS delta sigma dac problem on spartan 3e

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Hello,

 

I'm having a problem using the xps delta sigma DAC core on a spartan-3e starter board.  When Read_en is pulsed the DAC_out sends 1 short pulse and then nothing.  The length of the DAC_out pulse is proportional to the value that should be converted but the output stops when it should be sending a continuous pulse train.  I have Dac_clk_en high continuously when this happens.  

 

The DAC output of the ADC works exactly as it should so I have no problem with the ADC.  I just can't get the DAC to work in a useful fashion. 

 

I'm see the same behavior in systems built with OPB and PLB busses. 

 

Has anyone else encountered this problem?

 

Thanks
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10-13-2008 12:22 PM
1 Solution

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Anonymous
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With some help from xilinx tech support I have solved my problem. 

 

Driving the read_en signal directly from a GPIO does not work.  The usage of this signal by the core is such that the Read_en must stay active for exactly 1 clock period.  To make this the case I created a digital one shot from two instances of the Utility Flip-Flop cores.  The first stage clock is driven by my GPIO and the second stage is driven by the bus clock.  I have included a connection diagram below:

 

 

 

This circuit generates a pulse that is one clock period long every time the GPIO is asserted.  The DAC now seems to work just as I expected it to.

View solution in original post

one-shot circuit.bmp
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Anonymous
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I'm having the same problem, except I don't see any DAC_out activity. I haven't tried using the ADC.

 

I'm assuming that you're controlling Read_en (and DAC_clk_en) via gpio or something similar. Are you using the "Freeze" connection? I've tried it unconnected and constantly 0 without any change. I don't see it mentioned in the data sheet, however, which is odd.

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Anonymous
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I am driving both the Read_en and DAC_Clk_en with GPIO lines.  I also tried using the Freeze input and it seemed to make no difference whether it was driven via GPIO, tied to ground, or disconnected.  The only reference I found to the Freeze input was in the data sheet for the OPB version of this core which states that the Freeze input is unused.
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Anonymous
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I find it odd that you're seeing at least some DAC_out activity, rather than nothing (which is what I'm seeing). Our hardware setup seems to be roughly the same, so perhaps it's a software issue? Is your code based on low-level example provided by Xilinx?
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Anonymous
Not applicable
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With some help from xilinx tech support I have solved my problem. 

 

Driving the read_en signal directly from a GPIO does not work.  The usage of this signal by the core is such that the Read_en must stay active for exactly 1 clock period.  To make this the case I created a digital one shot from two instances of the Utility Flip-Flop cores.  The first stage clock is driven by my GPIO and the second stage is driven by the bus clock.  I have included a connection diagram below:

 

 

 

This circuit generates a pulse that is one clock period long every time the GPIO is asserted.  The DAC now seems to work just as I expected it to.

View solution in original post

one-shot circuit.bmp
phuijse
Newbie
Newbie
11,466 Views
Registered: ‎06-01-2009

Hello dhermann, are you driving Dac_clk_en with another GPIO or you leave it high?

 

im using your hint to drive Read_en but i still cannot succesfully use the delta sigma dac core.

 

could you point any errors en my code please?

 

#include "xgpio_l.h"
#include "xdsdac_l.h"

#define DSDAC_BASE_ADDRESS 0xca800000

 

 int main(void){

    XGpio_Initialize(0x81440000, 0);
    XGpio_mSetDataDirection(0x81440000, 1, 0x0);
   
    XGpio_Initialize(0x81480000, 0);
    XGpio_mSetDataDirection(0x81480000, 1, 0x0);

 

    //Here I enable the Dac by writing 1 to Control register

    u32 Register = XIo_In32(DSDAC_BASE_ADDRESS + XDAC_CR_OFFSET);
    Register |= XDAC_CR_EN_MASK;
    XDsDac_mWriteReg(DSDAC_BASE_ADDRESS, XDAC_CR_OFFSET, Register);
   
    //Here I write a value in the fifo
    Xuint16 nuevo = 1000;
    XDsDac_mWriteReg(DSDAC_BASE_ADDRESS, XDAC_FIFO_OFFSET, nuevo);

    //Here I read de value i just copy but it returns 0
    asd = XDsDac_mReadReg(DSDAC_BASE_ADDRESS, XDAC_FIFO_OFFSET);
    xil_printf("\r\n%d",(Xuint16)asd);

    //Here I read de occupancy register, and it returns 1
    asd = XDsDac_mReadReg(DSDAC_BASE_ADDRESS, XDAC_OCCY_OFFSET);
    xil_printf("\r\n%x",asd);

//This GPIO is to drive de flipflops for Read_en
    XGpio_mSetDataReg(0x81440000, 1, 0x0);
    XGpio_mSetDataReg(0x81440000, 1, 0x1);
    XGpio_mSetDataReg(0x81440000, 1, 0x0);
   
//This GPIO is to drive Dac_clock_en
    XGpio_mSetDataReg(0x81480000, 1, 0x0);
    XGpio_mSetDataReg(0x81480000, 1, 0x1);
    XGpio_mSetDataReg(0x81480000, 1, 0x0);
    XGpio_mSetDataReg(0x81480000, 1, 0x1);
    XGpio_mSetDataReg(0x81480000, 1, 0x0);

im sure that the gpio directions are ok also gpio's are correctly initialized.

Is there any special constraint for the external pin that im using for de dac output??

could you show me the line of thar pin in your ucf file please

 

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Anonymous
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In my application I just left dac_clk_en high because I had no reason to ever disable it. 

 

As far as your code, I don't see any use of the API calls that initialize and enable the DAC.  It appears that you are trying to manipulate the control registers at a low level which I never got in to.  I would suggest making sure you call the XDsDac_Initialize() function to make sure the DAC is properly initialized and XDsDac_Start() to start the DAC.  

 

The result you are seeing leads me to believe the DAC is not getting started properly.  You write a sample to the FIFO but the occupancy stays at 1.

 

Once you get past this step there is another feature to this DAC that could be unfortunate for you depending on your application.  When the FIFO empties the DAC output goes to zero instead of maintaining the last output value.  This means you will have to continually feed data to the FIFO and avoid underflow conditions if you want to maintain any kind of analog output.  

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fabiend
Contributor
Contributor
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Registered: ‎07-22-2009

I have use also your solution for my DAC (I produced a custom IP for having the good Read_En_output and I join Read_En_output (of my custom IP) with Read_En (of the DAC)) , but I don't understand how do you manage your GPIO Clk in your C program.

 

Indeed, in the DAC's datasheet, it says:

 

-1) Write dhe data to be converted into the Data FIFO.

-2) Enable the DAC by writing a "1" to the control register.

-3) Drive Read_en high for one SPLB_Clkm the value written into the Data Fifo will start being converted.

-4) If a new value is needed, write the new value into the Data FIFO.

 

So, your CPIO (input of the first clock's FIFO), has to be set in "1" after the two first operations each time you want to load a value.

 

But, how did you produce it ?How do you manage it ? Via your C program ?

 

Thanks for your help,

 

Best Regards,

 

Fabien

 

 

 

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take2czheng
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Visitor
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Registered: ‎11-17-2009

Can you guys tell me which FPGA pin can be used for DAC output using the XPS DeltaSigma DAC IP on the spartan-3e board?  From what I read, that IO pin needs an external lowpass filter.  Thanks alot in advance!

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fabiend
Contributor
Contributor
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Registered: ‎07-22-2009

Hi !

 

What is your board and FPGA ?

 

Best Regards,

 

Fabien D.

 

EDIT: Sorry I did not see in your first message. I am using a Spartan 3A DSP board, so it's not the same...

 

You could see here:

 

http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf

 

You have maybe access directly to different FPGA pins...And after you have to configure your UCF file corresponding to this pin.

 

Have a look on this document, Chapter 15...Maybe you will find what you are looking for.


Message Edited by fabiend on 12-08-2009 03:21 AM
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take2czheng
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Registered: ‎11-17-2009

Hi Fabiend,

 

Thanks for the reply.  I assumed that you guys were all using Spartan-3E board since it is the title of the thread.  I can not find a suitable GPIO pin in the schematic of the spartan-3e board that has external lowpass filter to use that pin for DAC.  Is there an external analog lowpass filter for the pin you are using in the spartan-3a board for the DAC purpose?  Which pin is that?  As you know, without the external lowpass filter, you will get all these spectrum images.   Just to be clear, I am not talking about using the on-board Linear Tech DAC/ADC; I am talking about implementing DAC using Xilinx IP.

 

Many thanks,

 

Charles

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fabiend
Contributor
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Registered: ‎07-22-2009

Hi,

 

On my board (Spartan 3A 3400 DSP), I used the soft touch connector:

 

On page 21:

http://www.xilinx.com/support/documentation/boards_and_kits/ug498_s3a_3400_board.pdf

 

I soldered a wire for example to the soft touch pin "A1", and I connect my low pass filter.

 

In my project file, in EDK, I created a new and external connection for the dac_output. And connect in my UCF file I connect this dac_output tothe FPGA pin "H2" (corresponding to the soft touch pin "A1").

 

So, you can try to find a pin you don't use, for example a FMC connector or something else, and solder a wire on it connect to your low pass filter.

 

Best Regards,

 

Fabien

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take2czheng
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Registered: ‎11-17-2009

I got it.  Thanks for the help, Fabiend.

 

Charles

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