I am using a XUPV5-LX110T Board (same as ML505 with bigger FPGA) and come across a problem I am not able to solve at the moment.
I tried to implement a design using the equipped 256MB DDR2 RAM and generate an interface with the CoreGen MIG tool. Everythings works fine until I need to assign the pins. I can´t select the right pin (K29) for the WE signal, because it is not listed in the signallist. I had a look into the schematic and saw that WE of the DDR2 socket is connected to pin K29, but pin K29 is marked as IO_L4N_VREF. I think that is the problem. So how to connect the right signal? I tried to connect WE somewhere else and later change the generated UCF file, but that did not work.
I think there must be a solution, because DDR2 with Microblaze in an EDK design works fine.
Development Environment: Xilinx ISE 13.1 on Linux 64Bit