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Participant
Participant
499 Views
Registered: ‎01-27-2017

ZCU104 Documentation missmatch

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Hello There,

I may have found a problem in pin assignment in the documentation provided by Xilinx for ZCU104 evaluation kit (https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0093-zcu104-evaluation-kit-hub.html)

For instance:

- The ug1267-zcu104-eval-bd.pdf specifies DDR4_SODIMM_DQ0 assigned to AG14 pin.

- The ZCU 104 schematic specified DDR4_SODIMM_DQ0 assigned to AE24 pin.

The others pins assignment does neither look consistent.

Can any Xilinx employee confirm if I missunderstood something or if there is a problem in the documentation?

 

1 Solution

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Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎03-21-2018

Re: ZCU104 Documentation missmatch

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Hi @xmartin 

This is a discrepancy in documention. A CR has been filed to fix this issue. The correct pin assignment for DDR4_SODIMM_DQ0 is AE24.

Cheers


Cheers
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Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎03-21-2018

Re: ZCU104 Documentation missmatch

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Hi @xmartin 

This is a discrepancy in documention. A CR has been filed to fix this issue. The correct pin assignment for DDR4_SODIMM_DQ0 is AE24.

Cheers


Cheers
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Visitor
Visitor
124 Views
Registered: ‎05-18-2019

Re: ZCU104 Documentation missmatch

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Hi,

 

Even I observe the same mismatch even now. There is no relation between PL-DDR4 pinout in schematics and PL-DDR4 pinout in the ZCU104 User guide. Whether we need to follow schematics or user guide?

 

With Regards,

HPB

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