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Observer
Observer
8,149 Views
Registered: ‎06-24-2013

iBERT DESIGN - ZC706 quad_111

Hello sir,

 

Thanks for the help so far.I am working ZYNQ family ZC706 board

 

I am actually trying to generate IP core for QUAD_111. I got struck at point,choosing the clock 

 

How much should I select the refernce clock frequnecy if i want to run GTX transceivers at 5 gbps or 6.6 0r 10 . the Gtx SMA clock is connected to QUAD 111. and what should i Specify REFclock source . should i go for MGTREFCLK1_112?

 

As per the few discussions i feel it.

 

Can you please answer the same things for quad_109 and quad_110 

 

suppose if i want to run gtx transceivers at 5 or 6 or 10 gbps ? what is the reference frequency should i specify?

 

what is Rference clock source ?MGTREFCLK1_?

 

can i also know how to decide the data port width? we usually select the 40 ..

 

 

thank you so much 

 

please help me in this regard

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2 Replies
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Xilinx Employee
Xilinx Employee
8,144 Views
Registered: ‎07-31-2012

Re: iBERT DESIGN - ZC706 quad_111

Hi sahitya,

 

Have you thought of or have used the "GT WIzard". Because this is something which you clear all the queries which you have.

 

Open the Coregen tool(ISE) or IP Catalog(Vivado) and check for "7 series FPGA transceiver wizard". This should help you decide the Reference Clock, Width, clock sharing and line rate.

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Moderator
Moderator
8,136 Views
Registered: ‎02-16-2010

Re: iBERT DESIGN - ZC706 quad_111

In IBERT GUI, you will have option to chose different REFCLK frequencies based on the line rate.

If you are able to provide a external clock, please select REFCLK location for SMA input clock otherwise chose the location as on board REFCLK which is routed to GTX.
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