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Registered: ‎10-02-2019

lowest phase noise configuration with series 7 FPGAs

Hello, 

I have to measure absolute phase noise of a frequency divider in the range of 160dBc @ 1kHz, so i need to create with FPGA a reference clock in the range 100-200MHz with the lowest possible phase noise.

Is there any reference design or application note that helps to correctly choose external clock hardware and FPGA pll implementation?

Thank you very much

Best regards

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