UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor donwaltman
Visitor
8,528 Views
Registered: ‎01-04-2011

spartan 6 output drive

Jump to solution

       I'm using the SP605 and getting very slow slew, i.e. rise and fall times of over 2uS where I cannot even drive a serial clock to one input at 800k.  I first was trying to drive the SCLK input on Maxims 11040 ADC on their Spartan6 daughter card.  I then rerouted the output to header J5 on the SP605 where the output is level shifted by U52, TXB0108 with little change.

       I then instantiated an OBUF with no change.  Then I put the following attributes info the UCF:

 

IOSTANDARD = LVCMOS15   (I used LVCMOS33 when driving the MAX11040)

DRIVE = 16

SLEW = "FAST"

 

No change.  I also have the same problems on my other outputs, CS and DOUT.  I would almost think the chip or board is faulty, but there may be something I'm missing.  Can anyone help?

 

Thanks, Don

 

0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
9,842 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

To sum up, after 29 posts in this thread:

 

The appearance of a problem was due to either faulty scope probe or incorrect scope setting.

 

Agreed?  If this problem has been resolved, please mark the thread as 'solved'.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

0 Kudos
28 Replies
Professor
Professor
8,524 Views
Registered: ‎08-14-2007

Re: spartan 6 output drive

Jump to solution

A few things:

 

1) How are you measuring the rise and fall times?  It is possible for example to get

confused when looking at a digital oscilloscope when looking at periodic signals

while sampling at a slower rate than the signal bandwidth.

 

2) Have you looked at the Vcco to the driving banks?  If this has jumpers on your

board, make sure they're correctly configured to supply the proper voltage for the

standard you choose.  Just setting IOSTANDARD to LVCMOS33 does not magically

supply the pin with 3.3V.

 

3) Where are you scoping the signal with the slow rise time?  At or near the FPGA?

Can you break the connection to the load and see if the slew rate becomes fast?

 

-- Gabor

-- Gabor
0 Kudos
Visitor donwaltman
Visitor
8,516 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

1) The scope is sampling well above the clock rate- I plugged in a 2M square wave and viewed just to be sure.

 

2) It does seem like there could be a power supply issue, but there are no jumpers for such.  Also, I used 1V5 when alternately driving an onboard level shifter and got the same results on the output of the level shifter.

 

3) Originally the signal was routed directly to the pins of an ADC.  The pins are very small, would be hard to lift, so I rerouted the signal to the level shifter I mentioned in 2) above.  The FPGA output will neither drive the ADC pin or the level shifter pin without a ridiculous amount of skew.

 

Thanks for the help, but still stuck.

0 Kudos
Scholar austin
Scholar
8,511 Views
Registered: ‎02-27-2008

Re: spartan 6 output drive

Jump to solution

d,

 

What are you driving?  A large capacitive load will slow down an output...

 

You mentioned you also measured the output of a level shifter, and it was slow, too?  If everything is slow, then it isn't the FPGA.

 

To measure a 1ns rise time, you need (at least) a oscilloscope with a bandwidth of more than 3 GHz..

 

Often oscilloscopes are just too slow (limited bandwidth) to measure transistion times.  What is the badwidth of the oscilloscope you are using?  Are you using a scope probe with the same bandwidth specification?

 

http://en.wikipedia.org/wiki/Rise_time

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Instructor
Instructor
8,506 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

To measure a 1ns rise time, you need (at least) a oscilloscope with a bandwidth of more than 3 GHz.

 

You are right, of course, Austin...  but...

 

1.  350-500MHz bandwidth scope is good enough for most digital logic work (but not PCIe or SATA).

2.  The MAX11040 A/D has a max SPI clock rate of 20MHz.  Signal rise/fall times of 5nS should work fine.

3.  The measured risetime was 2uS.  A 10MHz scope is good enough to measure 2uS edges.

 

On the other hand:

4.  When checking for signal integrity issues (e.g. clock edges), a 10MHz scope isn't good enough.  A 500MHz scope is good enough for edges of signal with toggle frequencies of up to about 100-200MHz (you don't fall of a cliff, but you do slide down a not-so-slippery slope).

 

I mention this for the readers who might be scared away or discouraged because they don't have have a $45K scope (probes not included).

 

To donwaltman, and others:

 

There is probably something simple at fault, if you are seeing 2uS (sluggish) signal edges everywhere.

 

Do you have much experience designing and troubleshooting digital logic?  Without knowing you or your background, we could spend many many forum posts discussing scope setup, probe techniques, reading the fine manual and schematics, reviewing all the jumpers, etc. etc.  If you are inexperienced, then it is helpful to methodically review each of these steps.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
8,486 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

Ok, the problem is not the scope.  My THS720 is 100Mhz and my serial clock is 800k. 

I routed the signals to J55 of the SP605 for analysis and got distortion with huge rise and fall times.  The signals pass through the TXB0108 Level Translator prior to J55.  I went directly to the chip and found the FPGA outputs to be fine (rise time < 50nS with "slow slew") at the inputs of the TXB0108, but the corresponding signals on the output pins to be trash.

What is even weirder, is that I have a translator (MAX3002) on the Maxim ADC board that is doing approximately the same thing and therefore my signals are never making it to the ADC.

Both translators are auto-detect bidirectional.  Has anyone else had bad experiences with these things?  I checked all chip voltages including the enable.  Am I a moron that I can't get a level translator to work?  Then again these things should be so transparent that I'm not aware of them. 

Any comments concerning the functionality of these kind of chips would be helpful.

Thanks, Don Waltman

0 Kudos
Instructor
Instructor
8,480 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

Would you please re-summarise where you find rise/fall times to be excessively slow?

Does this only occur at the TXB0108 buffer, on the side which is not connected directly to the FPGA?

 

What signal/connections combinations seem to be OK?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
8,474 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

The FPGA side of the buffer is great.  The unloaded output side is crap.   Only 4 IOs out of 8 are used.  All 4 give me crap for output.  I have pics of input vs output waveforms that I could send tomorrow if needed.

0 Kudos
Professor
Professor
8,470 Views
Registered: ‎08-14-2007

Re: spartan 6 output drive

Jump to solution

Since this seems to be an issue with the level shifters, can you send a diagram of this

part of your schematic?  It is worth double checking that you meet the requirements of

the shifters, e.g. Vcca < Vccb, OE referenced to Vcca and active.  Note that the turn-on

time from OE is very long - 1 us.  Toggling OE could cause the sort of timing you see.

 

-- Gabor

-- Gabor
0 Kudos
Visitor donwaltman
Visitor
8,408 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

Page 4, Figure 1A, U5

0 Kudos
Visitor donwaltman
Visitor
8,085 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

I sent you the one on the Maxim ADC board.  Here is the TXB0108 on the SP605.  P44 of the user guide

0 Kudos
Instructor
Instructor
8,073 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

Here is the TXB0108 on the SP605.  P44 of the user guide

 

The SP605 User Guide does not include board schematics.  And it's only 17 pages long.

The TXB0108 buffers are on page 35 of the SP605 schematics.  They do not connect to the FMC/LPC connector.

The FPGA directly drives the LPC connector, no buffer involved.

The Maxim board has its own level translator, a MAX3002.

 

So...  probing the TXB0108 doesn't help much.  What signals were you probing, again?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Instructor
Instructor
8,072 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

From your initial post in this thread:

 

... I then instantiated an OBUF with no change.  Then I put the following attributes info the UCF:

 

IOSTANDARD = LVCMOS15   (I used LVCMOS33 when driving the MAX11040)

DRIVE = 16

SLEW = "FAST"

You should drive the Maxim daughter board directly from the FPGA, using LVCMOS25 IO standard.

Except for the (3.3V, open-drain) I2C SCL/SDA lines.

 

All the interface signals are buffered on the Maxim card, expecting 2.5V swings.

 

The Spartan-6 IO bank which connects to the LPC connector has VCCO=2.5V, which is correct and consistent with the Maxim daughter card.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Professor
Professor
8,066 Views
Registered: ‎08-14-2007

Re: spartan 6 output drive

Jump to solution

The SP605 User Guide does not include board schematics.  And it's only 17 pages long.

The guide he posted is the wrong one.  You need the SP605 Hardware User Guide, p.44 which

shows some GPIO to a 6-pin header.  The level shifter appears to be on all the time (provided

that the supplies are connected as in the diagram - many eval kits have jumpers in line with

the bank supplies).  However there are also 200 ohm series resistors on each output wire,

which could server to slow the circuit down more.

 

-- Gabor

-- Gabor
0 Kudos
Visitor donwaltman
Visitor
8,064 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

You are right, the TXB0108 is irrelevant to my application.  I only referred to it because I discovered that it also had nearly the same problem when I used the J55 connector for troubleshooting.  What are the chances of having to separate level shifters that don't work?  I wanted to see if anyone else could possibly see any common denominators.

0 Kudos
Instructor
Instructor
8,062 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

I wanted to see if anyone else could possibly see any common denominators.

 

Let's re-establish the baseline.

 

What IO Standard and drive level are you selecting for FPGA output pins which directly connect to the LPC connector (and more specifically, the outputs among the 8 non-I2C signals used by the Maxim board)?

 

And what do you measure for rise/fall time on these 8 signals?  Do all 8 have similar rise/fall times?

 

Have you measured and verified the supply voltages on the Maxim board?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
8,061 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

The outputs to the TXB0108 are unloaded except for the scope so the series R shouldn't matter.  I suppose I will get a new maxim eval board and hope it works.  I'm tempted to jump over the max3002 level shifter and go directly to the 3.3 ADC with 2.5V, but I'm afraid of damaging the FPGA. 

0 Kudos
Instructor
Instructor
8,059 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

I'm tempted to jump over the max3002 level shifter and go directly to the 3.3 ADC with 2.5V, but I'm afraid of damaging the FPGA.

 

This is a lot of work, and it's too easy to break something.  I would suggest troubleshooting the straight-stick standard configuration.  It's not that complex, and if you were convinced that the Max3002 was broken you wouldn't be posting this thread.  Right?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
8,057 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

I'm currently using 8mA drive with slow slew.  There are three signals output from the FPGA- SCLK, CS and DOUT.  All are distorted (after the shifter), e.g. my 800khz serial clock never reaches zero and is nearly indistinquishable because of the skew. 

0 Kudos
Visitor donwaltman
Visitor
8,021 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

I don't see any other possibilities other than a broken 3002 except maybe a broken 11040 ADC.  However, Maxim like Xilinx is a reputable company and they don't put out trash, so I'm hestitant to rest on those conclusions.

0 Kudos
Professor
Professor
7,377 Views
Registered: ‎08-14-2007

Re: spartan 6 output drive

Jump to solution

@donwaltman wrote:

I don't see any other possibilities other than a broken 3002 except maybe a broken 11040 ADC.  However, Maxim like Xilinx is a reputable company and they don't put out trash, so I'm hestitant to rest on those conclusions.


 They probably weren't trash when they left Maxim.  It is possible that the 3002 was damaged by ESD

or momentary power supply overvoltage.

 

-- Gabor

-- Gabor
0 Kudos
Instructor
Instructor
7,375 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

I'm currently using 8mA drive with slow slew.  There are three signals output from the FPGA- SCLK, CS and DOUT.  All are distorted (after the shifter), e.g. my 800khz serial clock never reaches zero and is nearly indistinquishable because of the skew.

 

After the MAX3002 shifter?  (it's important to be very specific in forum posts)

 

Did you verify the power supplies on the Maxim board?  All of them?

Next would be to probe the pins of the MAX3002 device.  After the supplies are verified.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Instructor
Instructor
7,371 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

It is possible that the 3002 was damaged by ESD or momentary power supply overvoltage.

The MAX3002 is rated for 15KV ESD tolerance.  That's pretty good.

 

Here's another thought:  very carefully inspect the MAX3002 device, at position U5 on the Maxim board.  Make sure it is marked MAX3002, and not MAX3000 or MAX3000E.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
7,370 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

I checked the supply for the VL side (2.5V) and for the VCC side (3.3V) and the enable (2.5V) directly from the pins on the chip.  The inputs and outputs were also read directly from the chip pins. 

There are no power supplies on the  Maxim board; it's all supplied from the Xilinx SP605.

Chip damage could have occurred, however I wouldn't think that all three in/outs would be damaged the same way and I have not powered the board externally, only from the SP605.

It almost seems like this bidirectional design may have its pecularities but I wouldn't think they would put it out there if it were that unreliable.

0 Kudos
Visitor donwaltman
Visitor
7,368 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

3002, did it

0 Kudos
Instructor
Instructor
7,362 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

3002, did it

 

Well, unless your scope inputs are set to 50-ohm input term instead of 1M-ohm, I have no brilliant ideas left.

 

If it was my board, I would fire up a soldering station and start lifting pins for further troubleshooting.  I wouldn't recommend that for anyone else.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Visitor donwaltman
Visitor
7,359 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

Well thanks for all the help.  It at least gives me some confidence that I'm not crazy.  Tomorrow when I get access to the fine tip iron, I may lift the SCLK ADC pin. 

It's only an $80 eval board, but my greatest fear is getting another one and the same freaking thing happening. 

Thanks again for the help.  I'll post any significant findings.

0 Kudos
Visitor donwaltman
Visitor
7,320 Views
Registered: ‎01-04-2011

Re: spartan 6 output drive

Jump to solution

     Just an update on the MAX3002 level changer where the input signals were steep-edged and square and the output was crap.  Bob Elkin had mentioned a scope probe, but the same probe had accurately measured the inputs and just to be sure I measured the resistance going into the scope through the probe and got about 10M.  After narrowly escaping state-mandated commitment, I tried another probe just for the hell of it.  The signal looked improved but still distorted.  I put the probe on 10:1 and got a perfect signal. 

    I'm guessing the original probe had a capacitive load, but I was still shocked that the load of a good probe on 1:1 was too much for this chip.  I guess the 6k output impedance was a clue. 

    I think the manufacturers should do a better job of specifically documenting this in their data sheets.

    Thanks to all who helped.

0 Kudos
Instructor
Instructor
9,843 Views
Registered: ‎07-21-2009

Re: spartan 6 output drive

Jump to solution

To sum up, after 29 posts in this thread:

 

The appearance of a problem was due to either faulty scope probe or incorrect scope setting.

 

Agreed?  If this problem has been resolved, please mark the thread as 'solved'.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

0 Kudos