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Visitor
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Registered: ‎07-14-2016

zc706 Si5324 does not output clock

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Hi everyone!

 

I am new to the Zynq development and ZC706 board. I am trying to set up a simple ethernet loopback over the sfp using a 1G copper SFP plug. Unfortunately the design does not work and after some time of debugging I have established that the sfp IP (Gigabit ethernet PCS/PMA from Xilinx) is held in reset (resetdone output was not asserted). In that case I decided to check clocks, so I measured the clock on the resistor R251 which gave exactly 125MHz which was expected. The same good results I observed measuring the difference of the signals after the capacitors C138 and C141. Unfortunately I didn't see any clock output on pins 29 and 28 of Si5324, which, after attenuating the jitter, should feed back my 125 MHz back to the FPGA and to the SFP IP.

 

My design is very simple. It consists of the 1G eth PCS/PMA example design (for getting the clocks and resets done right) with only few modifications which were to bring some signals outside of the example design module, like resetdone. I added MMCM for synthesizing 125MHz from the default clock which is 200MHz and some buffers here and there. I also looped back the GMII interface to see packets bouncing of the FPGA on the computer. Both VHDL sources are in the attachment.

 

I have also found two contradictory pieces of information in Si5324 datasheet and its family reference manual. The first one says in the reset pin description:

Active low input that performs external hardware reset of device.  

Resets all internal logic to a known state and forces the device reg-  

isters to their default value. Clock outputs are disabled during reset.  

The part must be programmed after a reset or power-on to get a  

clock output. See Family Reference Manual for details.  

This pin has a weak pull-up.

and in the family reference manual there is:

For ease of manufacture and bench testing of the device, the default register settings have been chosen to place  

the device in a fully-functional mode with an easily-observable output clock. Refer to the data sheet for your device.  

The more reasonable opinion is stated in the family reference manual, but at this point I don't know what to think.

 

Does the Si5324 need programming for it to work or not?

 

Thank you for all your help and have a nice day!


Maciej Kopeć

“People," Geralt turned his head, "like to invent monsters and monstrosities. Then they seem less monstrous themselves. When they get blind-drunk, cheat, steal, beat their wives, starve an old woman, when they kill a trapped fox with an axe or riddle the last existing unicorn with arrows, they like to think that the Bane entering cottages at daybreak is more monstrous than they are. They feel better then. They find it easier to live.”
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Visitor
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Registered: ‎05-04-2016

Re: zc706 Si5324 does not output clock

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For the VC709 eval board, that also has an Si5324, the device needed to be programmed.

Programming is across the I2C bus driven by the FPGA. This typically requires an embedded processor such as MicroBlaze as the procedure is not trivial.  There are many steps involving polling of status for various step completion.

For the VC709, there was an example MicroBlaze design that was written in 'C' that showed how to program the Si5324.

I went to Silicon Labs website and downloaded their dspllsim tool (PrecisionClock_EVBSoftware) that runs on my Win7 PC.

You enter various parameters for your clocks and it will generate the required register settings.

You then modify the 'C' code for the MicroBlaze to use these new values. This requires the SDK development tool.

There is a multi-step programming procedure called out in the Si5324 datasheet that has to be followed.

I have no idea if the "defaults" work, as the device clearly needs programming for correct operation.

Maybe there is an example design for zc706 that helps or allows for a way to manually program across the serial port.  There

was nothing like this for VC709.

 

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Visitor
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Registered: ‎05-04-2016

Re: zc706 Si5324 does not output clock

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For the VC709 eval board, that also has an Si5324, the device needed to be programmed.

Programming is across the I2C bus driven by the FPGA. This typically requires an embedded processor such as MicroBlaze as the procedure is not trivial.  There are many steps involving polling of status for various step completion.

For the VC709, there was an example MicroBlaze design that was written in 'C' that showed how to program the Si5324.

I went to Silicon Labs website and downloaded their dspllsim tool (PrecisionClock_EVBSoftware) that runs on my Win7 PC.

You enter various parameters for your clocks and it will generate the required register settings.

You then modify the 'C' code for the MicroBlaze to use these new values. This requires the SDK development tool.

There is a multi-step programming procedure called out in the Si5324 datasheet that has to be followed.

I have no idea if the "defaults" work, as the device clearly needs programming for correct operation.

Maybe there is an example design for zc706 that helps or allows for a way to manually program across the serial port.  There

was nothing like this for VC709.

 

View solution in original post

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Scholar
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Registered: ‎06-05-2013

Re: zc706 Si5324 does not output clock

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@fizyk The Silicon Labs Si5324 U60 pin 1 reset net SI5324_RST must be driven High to enable the device.

-Pratham

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Re: zc706 Si5324 does not output clock

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Thank you for all your suggestions!

 

@pratham You were right, this was one of my problems, I fixed it, checked that the reset is high, but still I can't see the clock on the output of the Si5324 device. The next check I would perform is the reference quartz output but actually I don't know how to perform this measurement properly using an oscilloscope. There is another question as well - is the Si5324 ready to output clock after driving reset signal high?


Maciej Kopeć

“People," Geralt turned his head, "like to invent monsters and monstrosities. Then they seem less monstrous themselves. When they get blind-drunk, cheat, steal, beat their wives, starve an old woman, when they kill a trapped fox with an axe or riddle the last existing unicorn with arrows, they like to think that the Bane entering cottages at daybreak is more monstrous than they are. They feel better then. They find it easier to live.”
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Observer
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Registered: ‎09-18-2013

Re: zc706 Si5324 does not output clock

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After resetting the Si5324 (duration > 1us), wait for the reset to be over (10ms) before

writing to it.  You can write values to the Si5324 and then read them back to verify that

you are indeed acessing the Si5324.   The Xilinx examples I've seen use the interrupt-driven

stuff from the XIIC library, however, you can also do it using only the polled routines

XIic_Send() and XIic_Recv().  If you're not sure the crystal ref is working, try reading the

Si5324 register 129 for the LOSX_INT indication.  Also check the LOS1_INT indication.

I don't know the zc706 board, but probably you can program the FPGA to copy the output (or

a dervied output) of the Si5324 to an SMA on the board you can observe with

a scope.  You can also try putting the Si5324 into "bypass" mode, in which case it should copy

its input to its ouput, as a double-check that your method of observation is correct.

You can poll register 130's LOL_INT to learn when the pll  in the Si5324 has locked.

 

 

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Registered: ‎07-14-2016

Re: zc706 Si5324 does not output clock

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Thank you, I've done all that, it turned out that the chip (Si5324) was broken. It also needed programming, as the first reply stated. Thanks for the help!

Maciej Kopeć

“People," Geralt turned his head, "like to invent monsters and monstrosities. Then they seem less monstrous themselves. When they get blind-drunk, cheat, steal, beat their wives, starve an old woman, when they kill a trapped fox with an axe or riddle the last existing unicorn with arrows, they like to think that the Bane entering cottages at daybreak is more monstrous than they are. They feel better then. They find it easier to live.”
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