08-20-2019 03:12 AM
I am trying to combine the data from 4 parallel channels into 1 serial channel with geeneral FIFO. The data from each of the 4 parallel channels is 4 ksps and coming at the same time. So I put 4 general FIFOs to buffer them. Then a state machines is used to read data from each FIFO in sequence. The FIFOs are set to be "First Word Fall Through".
The code is verified in the VHDL testbench. The generated project meets all the constrants. In real-time implementation, it works fine most of the time. However, the output data will be occassionly and randonly mis-alligned.
As the state machines is rolling in sequence (served as a address line control), the mis-allignment in the data line will be recovered quickly.
I used the same code in Spartan-6 and Spartan-3 before without any issues. It is the 1st time it is used in a Zynq chip, which is apparently more complex in routing and timing.
I guess the issue is related to some phase jitter between the read enable signal and the read clock signal to the FIFO. However, I cannot find a way to solve it.
Are there any suggestions on this issue, or any other better parallel to serial conversion solutions available? Thank you.
08-20-2019 03:21 AM
without seeing the code, not much we can say,
What monitoring do yo have on the FPGA's
do you ever try to read fomr themwhen they are empty , or write when full ?
Do the fifos have constant clocks into them, these are syncronous FIFO's , so need both clocks always.
08-21-2019 03:58 AM