UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer dmi_iii
Observer
177 Views
Registered: ‎09-02-2015

40G/50G High Speed Ethernet v2.5

Jump to solution

Dear Xilinx,

For what type of Ethernet frame the "Figure 2-8: TX Mapping" with timing diagram on p.20 of PG211 is presented? What do you mean by QTag Qtag Qtag Qtag and why Source Address (SA) is in front of Destination Address (DA), although according to Ethernet II Frame (see.attachment) the frame begins with Destination Address (DA) and follows with Source Address (SA).

 

Thanks.

EN-ethernet-frame-structure.jpg
0 Kudos
1 Solution

Accepted Solutions
120 Views
Registered: ‎11-17-2016

Re: 40G/50G High Speed Ethernet v2.5

Jump to solution

Hi,

The Qtag is the optional VLAN Tag (IEEE 802.1q). If the packet is VLAN tagged, this 4Byte field follows the Source address. Otherwise 2 Byte Ether_type follows Source address.

AXI bus operates in LITTLE_ENDIAN format, as far as I know. Consider the packet is VLAN tagged. The data bus is 128bit wide. So in the first clock cycle, the data appers as follows

tdata[47:0] => DA (6 Bytes)

tdata[95:48] => SA (6 Bytes)

tdata[127:96] => Qtag (4 Bytes)

 

This is why the data in the bus is shown as

 Qtag Qtag Qtag Qtag SA SA SA SA SA SA DA DA DA DA DA DA

(MSB)                                                                                          (LSB)

View solution in original post

0 Kudos
1 Reply
121 Views
Registered: ‎11-17-2016

Re: 40G/50G High Speed Ethernet v2.5

Jump to solution

Hi,

The Qtag is the optional VLAN Tag (IEEE 802.1q). If the packet is VLAN tagged, this 4Byte field follows the Source address. Otherwise 2 Byte Ether_type follows Source address.

AXI bus operates in LITTLE_ENDIAN format, as far as I know. Consider the packet is VLAN tagged. The data bus is 128bit wide. So in the first clock cycle, the data appers as follows

tdata[47:0] => DA (6 Bytes)

tdata[95:48] => SA (6 Bytes)

tdata[127:96] => Qtag (4 Bytes)

 

This is why the data in the bus is shown as

 Qtag Qtag Qtag Qtag SA SA SA SA SA SA DA DA DA DA DA DA

(MSB)                                                                                          (LSB)

View solution in original post

0 Kudos