02-06-2021 06:14 PM
Xilinx jesd204 IP is used to receive ADC data, and 8lane is selected when IP generation.
Pin pin fixed in gth129 and gth130 (FPGA model xczu9eg)
Real machine test found that the data of gth129 4lane was abnormal, and the test voltage was only about 600 MV.
The 4lane data of gth130 is correct, and the voltage test is about 800mv.
In order to test what causes the abnormal voltage, the following two experiments are done:
Test case 1: when only 4lane jesd204-IP is generated and pin pin is fixed on gth129, the voltage test is 800mv
Test case 2: using ibert test, whether the gth129 test alone or gth129 and 130 test at the same time, the voltage is about 800mv
I am very confused about the above abnormality. Which direction should I go to investigate?
The version of vivado is 2021.1
02-09-2021 12:58 AM
Hi @avcon_lee ,
I would recommend you to use IBERT design to verify the GT Part.
02-22-2021 10:22 PM
Thank you for your reminding. I checked the mapping report and found that 4lane was put on gth128.
Although I fixed the location of the pin in the xdc file，but in the file of jesd204_0_phy_gt.xdc, the position is also constrained.
After I removed the conflicting constraints, there was no problem.