When using axi_smart_connect IP, I found a problem.AXI SmartConnect Settings as shown in figure 1
The SI datat width is 32bits,MI data width is 128bits.To ensure that the DDR data stream is full bandwidth, I set PKT_W_THR and WSIZE.
Resource consumption
- 5.5 brams were used,so the internal data buffer is used 128 bits wide and 512 depth.
The test found that the data width corresponding to PKT_W_THR is 32bits, while the data bit width corresponding to WSIZE is 128bits.And the maximum set of PKT_W_THR can only be the same as WSIZE, so DDR cannot work at full bandwidth.
AXI SmartConnect MASTER Sequence diagram
As shown, if I could set PKT_W_THR = WSIZE x 4, M00_AXI would fill up the bandwidth.But PKT_W_THR cannot be set to a value greater than WSIZE. Maybe it's a bug !