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Observer john
Observer
216 Views
Registered: ‎05-17-2018

AXI Stream clock converter with FIFO

Hi,

I have an AXI-Stream FIFO connected to another vhdl module working at a different frequency, with an AXI-Stream clock converter between them to handle the clock domain crossing.

The AXI-Stream FIFO is filled with the words 0xa,0xb,..0xc by a CPU connected to its AXI-Lite port.

On the other side of the fifo, after the clock convertsion I see following timings:

screen.png

AXI_STR_TXD_* are the output signals of the fifo, while the rx_* are the signals after the clock converter.

It can be seen how the data output of the clock converter (rx_tdata) is not correct: even though tvalid and tready are both asserted, each word is present on the bus for a different number of clk cycles (e.g. 0xb is there for much longer than 0xc).

This is more or less what I would expect if the clock converter was simply synchronizing the signals form a clock domain to the other, with the two clocks asyncronous and the destination clock faster than the source clock. But this would make its output useless in its intended application.

Am I using the clock conversion core improperly? I know there is also a dual-clock "AXI-Stream data FIFO" that works well in this case, but I also need the AXI-lite port for the CPU.

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4 Replies
Scholar dgisselq
Scholar
196 Views
Registered: ‎05-21-2015

Re: AXI Stream clock converter with FIFO

@john,

Just a quick question which may or may not be related, but ... how long are you holding the AXI components in reset before releasing them?

Dan

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Observer john
Observer
191 Views
Registered: ‎05-17-2018

Re: AXI Stream clock converter with FIFO

The reset is asserted by a "processing system reset" core, its external reset input lasts 5 clk cycles of the slowest clock.

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Scholar dgisselq
Scholar
180 Views
Registered: ‎05-21-2015

Re: AXI Stream clock converter with FIFO

Xilinx recommends a minimum of 16 clocks of reset.  Can you see if that changes anything?

Dan

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Observer john
Observer
139 Views
Registered: ‎05-17-2018

Re: AXI Stream clock converter with FIFO

well that's weird, I can't reproduce this issue anymore. I don't remember exatly but I believe I just restarted vivado and regenerated the AXI fifo and clock converter.

Thanks anyway for your suggestion, I will extend the reset to comply with the suggested implementation practices.

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