10-16-2019 09:33 AM
I have an AXI-Stream FIFO connected to another vhdl module working at a different frequency, with an AXI-Stream clock converter between them to handle the clock domain crossing.
The AXI-Stream FIFO is filled with the words 0xa,0xb,..0xc by a CPU connected to its AXI-Lite port.
On the other side of the fifo, after the clock convertsion I see following timings:
AXI_STR_TXD_* are the output signals of the fifo, while the rx_* are the signals after the clock converter.
It can be seen how the data output of the clock converter (rx_tdata) is not correct: even though tvalid and tready are both asserted, each word is present on the bus for a different number of clk cycles (e.g. 0xb is there for much longer than 0xc).
This is more or less what I would expect if the clock converter was simply synchronizing the signals form a clock domain to the other, with the two clocks asyncronous and the destination clock faster than the source clock. But this would make its output useless in its intended application.
Am I using the clock conversion core improperly? I know there is also a dual-clock "AXI-Stream data FIFO" that works well in this case, but I also need the AXI-lite port for the CPU.
10-16-2019 10:30 AM
10-16-2019 10:36 AM
The reset is asserted by a "processing system reset" core, its external reset input lasts 5 clk cycles of the slowest clock.
10-16-2019 01:36 PM
well that's weird, I can't reproduce this issue anymore. I don't remember exatly but I believe I just restarted vivado and regenerated the AXI fifo and clock converter.
Thanks anyway for your suggestion, I will extend the reset to comply with the suggested implementation practices.