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betontalpfa
Explorer
Explorer
1,049 Views
Registered: ‎10-12-2018

AXI stream FIFO fill level toggles in reset

I have a AXI-Stream Data FIFO (aka. AXI4-Stream Interconnect in FIFO mode.)

I use it as clock converter too. So it has two clock and two reset input.

AXIS_data_FIFO.PNG

First question: what is the difference of the three data_count ports? I guess that axis_wr_data_count and axis_rw_data_count can be used in s_axis_aclk and m_axis_aclk's clock domain respectively.

But what is the aim the the native axis_data_count port?

Second question:

I monitor the data_counts with a chip-scope, and I realized, that the data_count can be 0x2 even if the either reset input (s_axis_aresetn, bs_axis_aresetn) of the FIFO is asserted.

More precisely the fill level togles between 0 and 2, when the input and output stream interfaces are in idle state. (The valid/ready signals are inactive.)

image.png

Zoom:

image.png

Pictures above has taken when I asserted the s_axis_aresetn input.

What is the root-cause of this behavior?

I use:

  • Vivado 2016.3
  • Win 7
  • 7series Virtex FPGA
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2 Replies
pthakare
Moderator
Moderator
1,039 Views
Registered: ‎08-08-2017

Hi @betontalpfa

From the IP settings it is clear that ,you are using Asynchronous clocking .The Axis_data_count indicates the count inside the DATA_FIFO  when Asynchronous clocks set to  "NO " i.e Common Clocking.

The detail Description of these outputs from Product guide.

Capture.PNG

 

    Capture1.PNG

Axis_data_count does not have any significance in Asynchronous Clocking mode. Can you please check Axis_wr_data_count and Axis_rd_data_count  outputs and let us know if you are observing any unexpected behaviour?

Additionally can you check in the simulation if the axis_data_count is also toggling between 0 and 2 when

when the input and output stream interfaces are in idle state and active state?

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betontalpfa
Explorer
Explorer
989 Views
Registered: ‎10-12-2018

I have opened the schematic, which shows, that the axis_data_count and the axis_wr_data_count is the same signal in my case.

image.png

 

 

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