cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
751 Views
Registered: ‎10-01-2010

Aurora 64b66b: Cannot use GTHQ9 in a 4-lane configuration, validation failed for parameter 'GT Refclk2'

I'm trying to use Aurora 64b66b in Vivado 2018.2 using the IP Integrator, targeting an XC7VX690T-FFG1927-2 (so all MGT banks are bonded). As shown in the screenshots, I've selected the four lanes in GTHQ9 but Vivado will not allow me to set these parameters. The customizaton GUI shows a red "None" for GT Refclk2 but won't allow me to change it to anything else. (I believe "None" should be the correct value since I'm only using one quad.)

 

When I hover over the setting or try to click OK, the IPI returns with the message:

 

Validation failed for parameter 'GT Refclk2(C_GT_CLOCK_2)' with value 'None' for BD cell 'aurora_64b66b_4'. Two clocks cannot possibly power the selected lanes.

 

Of course this is true and the settings reflect this, but Vivado flags this as an error and refuses to let me configure the core this way. Am I missing something or is this a bug?

 

GT selections (top)

GT selections (bottom)

Tags (2)
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
725 Views
Registered: ‎03-30-2016

Hello @tonyle

 

Those GTH are not bonded out.

XF_V7_GTH_not_bonded.png

 

Please ensure that you are selecting the correct device model

 

Thanks

Leo

 

0 Kudos
Highlighted
Contributor
Contributor
704 Views
Registered: ‎10-01-2010

The transcript indeed indicates I've selected the FFG1927 package:

 

INFO: [Device 21-403] Loading part xc7vx690tffg1927-2

 

In addition, Vivado has no problem with the clock assignment if I configure the core for 8 lanes:

 

GT selections (8 lanes)

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
687 Views
Registered: ‎03-30-2016

@tonyle

It seems you selected device model correctly (xc7vx690tffg1927-2). So all GTH should be fully-bonded.

Could you please try to generate your IP with GTHQ8 setting , and modified pin-assignment constraint manually ?

 

0 Kudos