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colombini_luca
Explorer
Explorer
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Registered: ‎11-05-2008

Aurora init/drp clock from IBUFDS_GTE2 ODIV2 output in Artix-7 ?

We are designing a chip2chip solution between a ZynqUS+ and Artix-7 device, using Aurora 8b10b.

We would like to use the link reference clock (125 MHz) as the source for either init and DRP clock input to AUrora IP.

So we have instantiated an IBUFDS_GTE2 macro and we have connected the ODIV2 output to INIT and DRP clock.

But we get a partially routed design with the following message::

[DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are design_1_i/aurora_8b10b_odiv2_0/U0/gt_refclk1.

The gt_refclk1 is the net connected to O output of IBUFDS_GTE2 instance.

The following command:

report_route_status -route_type partial

returns:

Partially Routed Nets:
design_1_i/aurora_8b10b_odiv2_0/U0/gt_refclk1
Unrouted Pins:
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllpd_quad0_wait_reg[31]_srl32/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllpd_quad0_wait_reg[63]_srl32/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllpd_quad0_wait_reg[94]_srl31/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllpd_quad0_wait_reg[95]/C
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllreset_quad0_wait_reg[126]_srl31/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllreset_quad0_wait_reg[127]/C
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllreset_quad0_wait_reg[31]_srl32/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllreset_quad0_wait_reg[63]_srl32/CLK
design_1_i/aurora_8b10b_odiv2_0/U0/gt_common_support/cpllreset_quad0_wait_reg[95]_srl32/CLK

 

Our design takes the "Aurora 8b10b with shared logic in example design" example design and we modified its ODIV2 output.

We remove any unneeded logic like traffic generators and checkers.

The modified example design has been converted into a custom IP and instantiated in the top block diagram:

 

top_bd.png

Do you see any impediment in using ODIV2 output as the clock source for init/drp clock of Aurora IP?

We use Vivado 2020.2. The modified example design is attached.

 

 

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4 Replies
rkhatri
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Registered: ‎01-10-2019

Hi @colombini_luca ,

Please refer to below link.

https://forums.xilinx.com/t5/Serial-Transceivers/IBUFDS-GTE4-output-drive-generic-logic-would-it-introduce-jitter/td-p/826535

 

Thanks,
Rahul Khatri
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colombini_luca
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Registered: ‎11-05-2008

Hi @rkhatri ,

  IBUG_GT is not supported on Artix-7 family.

  The project which gives us issues is on the Artix-7 side.

 

 

 

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rkhatri
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Registered: ‎01-10-2019

Hi @colombini_luca ,

I think you can use BUFG.

rkhatri_0-1612941256752.png

 

Thanks,
Rahul Khatri
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colombini_luca
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Registered: ‎11-05-2008

Hi @rkhatri ,

 here you can find the complete project: https://nuvola.caen.it/index.php/s/srN4ns75IXGs675

 If you open the test-odiv2/vivado/design_1.xpr and compile to bitstream, you will get the error message:

  [DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are design_1_i/aurora_8b10b_odiv2_0/U0/gt_refclk1.

  I have instantiated a BUFH in this case, but the result is the same with BUFG.  

How do you explain this issue?

   I can bypass this issue by commenting away the piece of code in ip_repo\aurora_8b10b_odiv2\src\aurora_8b10b_0_gt_common_wrapper.vhd (see -- HACK LCOL comment)

    and uncommenting the following two lines. 

    But then the design doesn't work when connected with the other Chip2chip instance on the other side of the link.

     Can I use IBUFDS_GTE2.odiv2 output to drive chip2chip init_clk and drp_clcock, and my logic, for instance by using the  init_clk_out port?

Thanks,

Luca

  

 

  

 

 

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