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Visitor
Visitor
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Registered: ‎06-17-2020

Auroura 64B66B Transceiver Setup

Hello,

I am trying to quickly setup a loopback configuration for my part (xczu15eg-ffvb1156-1-i) using the Aurora 64b66b IP in Xilinx Vivado 2019.2 for the Zynq Ultrascale+. I was wondering if Xilinx has any example designs that use the transceiver capabilities of the aurora 64b66b IP. Namely, information on how to setup the transceiver/clock/reset/etc pins properly (in the vhdl architecture and block design). If nothing exists for my current setup, are there any example designs for different part/FPGA combinations that I could build off of?

Kindly,

Anvar Akhmedov

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Moderator
Moderator
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Registered: ‎01-10-2019

Hi @aakhmedov ,

Please refer to "example design" Section of PG074. 

Thanks,
Rahul Khatri
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Visitor
Visitor
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Registered: ‎06-17-2020

I setup a design using Xilinx Aurora 64B66B IP as well as my own waveform wrapper IP (migrated from Vivado 2015.4). I didn't get any errors during synthesis or implementation. But upon analyzing my implementation, I can see that the tx connections are not setup. It seems that the rx connections are created however. The log file associated with this run is attached.

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Visitor
Visitor
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Registered: ‎06-17-2020

I am attaching an image of my implementation. You can see that that receive side pins are connected (on left) but the transmit side isn't connected at all.

Screenshot from 2020-06-29 13-26-17.png

 

Screenshot from 2020-06-29 14-27-08.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

Please check the source codes to confirm if the top modue output pins TXP/TXN are connected to GT submodule TXP/TXN finally.

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