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Harish_Algat
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Registered: ‎06-04-2020

BLOCK ROM

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How I generate 2046*64 BLOCK ROM ?

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pthakare
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Registered: ‎08-08-2017

Hi @Harish_Algat 

You have below options

#1 Use the block memory Generator IP under the IP catalog.

Capture.JPG

#2 Use the XPM_MEMORY_SPROM macro. Instantiation is available in UG974 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug974-vivado-ultrascale-libraries.pdf

#3 use the inference method , refer to synthesis user guide UG901

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

With these method you will be able to implement the ROM using block RAM resources in the device.

 

 

 

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pthakare
Moderator
Moderator
508 Views
Registered: ‎08-08-2017

Hi @Harish_Algat 

You have below options

#1 Use the block memory Generator IP under the IP catalog.

Capture.JPG

#2 Use the XPM_MEMORY_SPROM macro. Instantiation is available in UG974 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug974-vivado-ultrascale-libraries.pdf

#3 use the inference method , refer to synthesis user guide UG901

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

With these method you will be able to implement the ROM using block RAM resources in the device.

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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pthakare
Moderator
Moderator
507 Views
Registered: ‎08-08-2017

Hi @Harish_Algat 

You have below options

#1 Use the block memory Generator IP under the IP catalog.

Capture.JPG

#2 Use the XPM_MEMORY_SPROM macro. Instantiation is available in UG974 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug974-vivado-ultrascale-libraries.pdf

#3 use the inference method , refer to synthesis user guide UG901

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug901-vivado-synthesis.pdf

With these method you will be able to implement the ROM using block RAM resources in the device.

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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Harish_Algat
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Registered: ‎06-04-2020

I am not able to edit that option that is why I have raised the query I am using 2019.2 vivado.

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Harish_Algat
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Participant
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Registered: ‎06-04-2020
Hello I am not able to edit these options
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pthakare
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Moderator
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Registered: ‎08-08-2017

Hi @Harish_Algat 

Share your IP Screenshot?

Are you using the BRAM controller mode ? If so the parameters are propagated from master .

Please check the product guide

https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf

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Harish_Algat
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Registered: ‎06-04-2020
That solved my problem...Can you tell me how can I implement 8K*64 Block ram
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