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Observer
Observer
951 Views
Registered: ‎05-22-2018

BRAM (AXI) read burst reads first address twice

Hello Xilinx community,

I've got an issue with my BRAM logic, created with the Block Memory Generator v8.4.

I've written data to my BRAM in the following manner:

Selection_002.png

 So that the data gets changed for every clock cycle until all 32 burst cycles are complete. So far no problems in sight.

 

When I try to read the data the following behaviour occurs:

Selection_001.png

As you can see, when I'm reading the data with single bursts, the right data is transferred. Whenever more than 1 data is read, the data of the first address gets read twice.

 

I have no clue, why this happens, as the write process functions properly. Is there any delay that needs to be taken into account or is the first data packet invalid in any case? I would appreciate any hints.

 

h89w43hilz

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Instructor
Instructor
569 Views
Registered: ‎10-23-2018

@h89w43hilz

Did you ever resolve this? If not, is it possible to post you code and testbench?

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