I have designed a small dual port buffer (200x9bit) using BRAM. I have instantiated and used this buffer in another module(PM module). Finally i have instantiated 16 PM modules in a Top module of my design. Vivado had used 16 BRAM block for this design. Is there a way to share the one or two BRAM for all 16 buffers? I am looking for a directive in XILINX Vivado.