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kvantum.nuly
Contributor
Contributor
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Registered: ‎11-09-2017

BRAM width PORTA vs width PORTB

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Hi all,

I use PORTB as external port (out of block design), but maximum width in IP configuration is 128 bit width (I need 256 bit width). It there some limits for ratio between PORTA width and PORTB width? 

bram_problem.PNG

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vemulad
Xilinx Employee
Xilinx Employee
1,991 Views
Registered: ‎09-20-2012

Hi @kvantum.nuly

 

This limitation of 4:1 aspect ratio is due to byte write feature. 

 

[IP_Flow 19-3478] Validation failed for parameter 'Read Width B(Read_Width_B)' with value '32' for BD Cell 'blk_mem_gen_0'. The ratio between two data widths must not exceed 4:1 when byte writes are enabled

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
1,992 Views
Registered: ‎09-20-2012

Hi @kvantum.nuly

 

This limitation of 4:1 aspect ratio is due to byte write feature. 

 

[IP_Flow 19-3478] Validation failed for parameter 'Read Width B(Read_Width_B)' with value '32' for BD Cell 'blk_mem_gen_0'. The ratio between two data widths must not exceed 4:1 when byte writes are enabled

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

kvantum.nuly
Contributor
Contributor
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Registered: ‎11-09-2017

Thanks for your reply! 

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