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Observer alen89
Observer
271 Views
Registered: ‎06-26-2019

Block memory generator in mode true dual port

Dear,

I am using block memory generator 8.4 to instanciate a true dual port ram in stand alone mode over an ultrascale device(XCZU3EG).

I am using a bram axi controller in port A and user defined in port B. I simulate the design with modelsim and the write and the behaviour of the FSM that I am using to write work properly. But when I generate the binary files I neve see nothing written in the memory. I always can write and read from the port that is connected to the mpsoc but never with the FSM.

What could it be the problem?.

Find attached also the captures of configuration.

Best,

Alen.

mem_gen1.jpg
mem_gen2.jpg
mem_gen3.jpg
mem_gen5.jpg
schematic.jpg
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5 Replies
Moderator
Moderator
238 Views
Registered: ‎08-08-2017

Re: Block memory generator in mode true dual port

Hi @alen89 

The first debugging step should be to add bebug probes and monitor if proper transactions happening on below signals or not

doutb 
addrb 
dinb 
web 

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Observer alen89
Observer
229 Views
Registered: ‎06-26-2019

Re: Block memory generator in mode true dual port

I did already, in fact I have a debug port to check if the FSM is moving on states.. And when I dump the ram I saw 2 positions written.. but not the good ones.. Could be that is not enough for write one clock cycle?..
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Teacher drjohnsmith
Teacher
227 Views
Registered: ‎07-09-2009

Re: Block memory generator in mode true dual port

you have simulated , which is a great place to start, amazing how many people dont,
Second up is do you have timing constraints and are they meet ?
If not, you need to fix that first, no point going to hardware with out constraints, or broken constraints,
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Observer alen89
Observer
219 Views
Registered: ‎06-26-2019

Re: Block memory generator in mode true dual port

"you have simulated , which is a great place to start, amazing how many people dont"
if not at least me, I could become crazy if I dont simulate :D
"Second up is do you have timing constraints and are they meet ?"
The report timing does not complain nothing about the ram or the modules related to this part of the design.. I am trying with a simple fsm to check..
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Teacher drjohnsmith
Teacher
173 Views
Registered: ‎07-09-2009

Re: Block memory generator in mode true dual port

do i take it u do have timing fail then,

fix that first
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>