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Explorer
Explorer
522 Views
Registered: ‎09-08-2009

Bram Simulation Read Delay is 2 cycles instead of 1

 

I expect the 3F03F851 to appear on Doutb 1 clock cycle early (true dual port ram, no output register, common clock, write first, always enabled) 

It does not appear in the same cycle , it does not appear in the next cycle, it appears on the 3rd cycle.

clock cycle 1 : 3F03F851 is written to bram address 101 (red circle)
clock cycle 3:  Data output is 3F03F851 (yellow circle)




bram_sim_read_delay.png
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Bram Simulation Read Delay is 2 cycles instead of 1

The Data is read 1 clock  after writing. The red circle is not around a rising edge. The write occurs at 9090ns, and read at 9100ns.

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Explorer
Explorer
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Registered: ‎09-08-2009

Re: Bram Simulation Read Delay is 2 cycles instead of 1

 

@richardhead thanks for your input. 

if the first rising edge clock that write en is 1 : is at orange rising edge clock , then
   the first rising edge clock that read data is available : is at pink rising edge clock

still 2 clock cycles. or am I reading this wrong?

I think

  • if the data is already in the memory read delay is 1 clock cycle, 
  • if the data is not in the memory read delay is 2 clock cycles , like this example. 

 

 I started this post since : I am writing data to a memory in the first clock cycle (keeping the read address same with write address), in the second clock cycle I use the read data and do another operation, and the result is wrong. 

 

bram_sim_read_delay_v2.png
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Explorer
Explorer
350 Views
Registered: ‎09-08-2009

Re: Bram Simulation Read Delay is 2 cycles instead of 1

what I have (1ST SCREENSHOT because I use 7 series, True Dual Port Ram, Port A : Write First)

According to first screenshot from https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

if I write DIA to Port A then resulting data out port B is X

 

what I want (2ND SCREENSHOT, correct for SDP)

According to second screenshot from https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf

if I write DIA to Port A then resulting data out port A is DIA

 

true_dual_port_ram_7series.png
sdp.png
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Moderator
Moderator
297 Views
Registered: ‎08-08-2017

Re: Bram Simulation Read Delay is 2 cycles instead of 1

Hi @999068709169 

I have SR for this issue , As mentioned on SR mail thread

The write mode attribute can be individually selected for each port. WRITE_FIRST outputs the newly written data onto the output bus.

Here you can see the input data is simultaneously written into memory and stored in the data output (transparent write).

 

Please refer to UG583  https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf page 13 for Write modes.

 

temp1.jpg

 

The below table shows the resulting data out PORTA/B when there is address collision.

 

i.e when you have true dual port memory configured and Write mode of PORT A is set to Write first , and Write mode of Port B is Read_first/write_first/no change

In the configuration if you are trying to write from PORTA and read from PORTB , the resulting Data out PORTA is DIA as per above timing diagram and resulting Data out PORTB is “X”

 

temp2.png

Now coming to your question ,

While reading from memory , this write modes don’t have any significance , with no output register selected , you should get the data out after one clock cycle.

 

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Moderator
Moderator
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Registered: ‎08-08-2017

Re: Bram Simulation Read Delay is 2 cycles instead of 1

Hi @999068709169 @richardhead 

The resolution is already provided to customer on service request .

Here is the resolution for your information

when I checked the XCI , you have collision warning selected for structural simulation and disable collision warning for behavior simulation.

 

 

col1.jpg

 

 

Looking at the below capture you are trying to write and read from address “101” and hence it is read-write collision.

 

col2.png

 

In this configuration write will be successful but data on output B after inherent latency will be “X” and in next clock cycle there is no address collision and you will be getting data at address “101”

After one clock cycle inherent latency .

So looking at the overall picture it is 2 clock cycle latency in case of address collision and it is correct behavior.

I will recommend you to re-run the simulation with collision warning selected to ALL or Generate “X” only  for structural simulation and don’t disable the collision warning for behavioral simulation to observe the “XXX” in output during  write-read collision.

Customer have tried this and observe the behavior expected.

first clock cycle XXX, 2nd clock cycle correct data on PortB doutB

col3.png

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Reply if you have any queries, give kudos and accept as solution
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