06-18-2019 09:12 PM
I have master and slave CPRI cores in my FPGA design. I am using KC705 board. The IQ data received from slave is fed to the master through a FIFO. In this case, does both the master and slave cores need to be given source synchronous clock?
If they dont need source synchronous clock, how to connect the synchronization interface?
I tried connecting the synchronization interface as mentioned in xapp1132. The master link is not stable? The clocks of the master seem fine. what can be the issue
06-19-2019 10:07 PM
If it's async, you need to cross clock domain in FIFO1/2 by yourself.
You can try stopping data first. Can Master link up? You can try GT near end PMA loopback. If Master still fails to link up, what is its stat_code?
06-30-2019 10:58 PM
That's exactly what my question is..
Do the reference clocks for cpri master and slave core need to be from the same source or not?
In my design, the cpri slave core works with (jitter cleaned)recovered clock as its reference clock. The cpri master core works with reference clock from crystal oscillator. If this is the case, will my design work is the question?
06-30-2019 11:11 PM
When the cpri slave core works with (jitter cleaned)recovered clock as its reference clock, this recovered clock sync to the received serial data (RXP/RXN) and the link partner's reference clock.
If the slave's link partner has the same reference clock source as the master, then it's also the synchronous design. And it should be OK.