07-20-2012 09:18 AM
Does any one know of a document which describes the byte ordering of the output with respect to that of the input for a Virtex 6 CoreGen generated Non-symmetric FIFO? I'm looking at the LogiCORE IP FIFO Generator v9.1 which is the data sheet for this device and aside from saying that it supports non-symmetric FIFOs there is little mention of non-symmetric details.
I kind of remember this was spelled out in an earlier CoreGen document for the FIFO for ISE v12.1 & Virtex 4 but it does not seem to be in the newer documentation.
07-20-2012 06:16 PM
When the documentation is non-existent or ambiguous, I generally simulate the core
with a simple test bench to see how it works. However, my recollection of earlier versions
of the asymmetric FIFO's is that they are Big Endian. i.e. if your write width is 32 and read
width is 8, then the first four reads will come from bits [31:24], [23:16], [15:8], [7:0] respectively.
I generally use little endian throughout my designs, and when using a FIFO for an asymmetric
application, I just generate a FIFO of the larger port width and add my own logic to handle the
assembly or disassembly of the smaller port data.
07-25-2012 10:52 AM
Thanks for your response. When I see something like that (such a blatant ovesight), I don't want to spend my time and money compensating for Xilinx's carelessness. I'd rather open a webcase and have them pay the price. Then maybe next time they will be better motivated to fix it.
09-17-2012 12:54 PM
Was searching for the answer myself, and found the answer in:
UG175, p124 and 125 in the 14.1 release, or search for "Non-symmetric Aspect Ratios".